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post #17371 of 28665
My confusion is where is this voltage applied. On the Cpu? I'll probally mix up HT and HTT till they day I die.

As I was trying to ask and BO did a good job of saying.
If this voltage is applied to Increase the signal strength between the mem controller (on die) and Memory then does this mean the CPU is capable of having multiple varying voltages applied to it (AKA Dual plane)? Or is this voltage applied to the bus some other way (AKA NB)? Because As I stated in my HTT ,misstated post If indeed the voltage is applied to the mem controller directly it would seem that this would lower the TPD If the Vcore was lower and the LTD/HT was bumped?
IF so I want this setting on my Mobo.
post #17372 of 28665
I believe it is applied in some other way. As far as I know, until the STARS processor (K10 or K10.5; requiring AM2+ not AM2) AMD were single plane processors. On my boards, the voltage setting did not help stability when Hypertransport was below 1000 MHz, so it should be for Hypertransport, not HTT.
     
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post #17373 of 28665
I don't see how a signal can be increased unless the voltage is increased on one end or the other. I would guess it would be on the cpu as the NB would need a repeater (which would cause all kinds of issues.
That or I am missing something blatantly obvious? These days I wouldn't be surprised.
post #17374 of 28665
For the life of me, I do not know WHERE the LDT voltage goes, but it goes somewhere. Increasing that voltage will permit you to keep a 5x Hypertransport multiplier at higher HTTs. I did not notice a CPU temperature increase, so I do not think it is there that the voltage is applied.
     
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post #17375 of 28665
Thx Blitz. I'd really like to know this one.
post #17376 of 28665
Have any of you guys looked at this Here for the explanation to LDT voltage right here in our own back yard
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post #17377 of 28665
You know I've been thinking about where the LDT voltage is actually applied. And the diagram for the ULi interconnections pops in to my head. I can't seem to locate it at the moment. But from an article I read earlier today, from what I gather about the LDT its the communication lanes between the peripherals and the CPU.
So that leads me to believe that the voltage must go to the southbridge which is what all of the peripherals go through with the exception of the PCIe slots. Thats why the PCIe lanes usually (on DFIs anyway) have their own voltage and frequency settings. Totally independent of the NB and SB.
But since there is no temp sensors on there, it's hard to tell.
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post #17378 of 28665
I scoped that out yesterday, still doesn't explain how a voltage appears on the bus.
Quote:
EDIT: power first goes to the HHT bus then is redirected from there to the memory controller, 9/10 you only need to increase the VDIMM if tightening timing
If this statement is correct then I would like to know how. And if it is the NB and not the CPU then would lowering the nb voltage while increasing the HT voltage allow for a higher HTT?
Neither of my boards have this option so I'm really intrigued now.
post #17379 of 28665
Hey BO do you have a link to the block diagram? The southbridge is direct connected to the mem lanes? I thought the NB deligated to the SB.
post #17380 of 28665
I posted it in here not too long ago, but you'd have to search to find it.

And I was under the impression that the LDT had nothing to with the memory whatsoever.
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