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[dvHW] Intel Nehalem slides - Page 2

post #11 of 15
If Junny1989 is right, then this is bad news


But seeing how good Intel is doing... whatever that 'restricting thing' is... can probably handle 4+GHZ....


Then we will simutaneously laf at AMD for.......nvm that

GO NEHALEM!
    
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post #12 of 15
Quote:
Originally Posted by jonny1989 View Post
Just look at that AMD chips, a lot of them OC like crap such as the Phenom Quads. And AMD chips have for some time now been hitting much lower overclocks than Intel chips.

I think its do to the fact that they have the on die memory controller. There adding more and more parts to the CPU, that’s more and more parts that have to handle the higher clock speeds.

And if say your LV3 cache or your on die memory controller can't take the speed then your limiting the rest of the CPU and will end up with a lower overclock
Not entirely true because the Phenoms have separate power planes for the cores and memory controller. The cores and the NB/L3 run at different speeds yet the cores still aren't OCing as well as we all hoped it to be.
    
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post #13 of 15
Quote:
Originally Posted by jonny1989 View Post
Just look at that AMD chips, a lot of them OC like crap such as the Phenom Quads. And AMD chips have for some time now been hitting much lower overclocks than Intel chips.

I think its do to the fact that they have the on die memory controller. There adding more and more parts to the CPU, that’s more and more parts that have to handle the higher clock speeds.

And if say your LV3 cache or your on die memory controller can't take the speed then your limiting the rest of the CPU and will end up with a lower overclock
I agree the on-die memory controller looks to be a suspect for the low clocks.

Quote:
Not entirely true because the Phenoms have separate power planes for the cores and memory controller. The cores and the NB/L3 run at different speeds yet the cores still aren't OCing as well as we all hoped it to be.
Sure it doesn't scale up like with RAM?
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post #14 of 15
Well if you can OC the Cores without dealing with the memory controller then I guess it would be fine, But I still think that adding an on die memory controller could lower the quality of the over all chip. Because even thow it's on the 45nm process it's still adding more parts to the chip and making a larger die size. Not only that but these will be native Quads so that could also affect yields and quality.

Plus once Intel gets their stupid graphics processor on die there will be even more crap I don't won't on my chip.

And I thought that Lv1, 2, and 3 cache ran at the same speed as the rest of the CPU?
    
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post #15 of 15
Quote:
Originally Posted by jonny1989 View Post
Well if you can OC the Cores without dealing with the memory controller then I guess it would be fine, But I still think that adding an on die memory controller could lower the quality of the over all chip. Because even thow it's on the 45nm process it's still adding more parts to the chip and making a larger die size. Not only that but these will be native Quads so that could also affect yields and quality.

Plus once Intel gets their stupid graphics processor on die there will be even more crap I don't won't on my chip.

And I thought that Lv1, 2, and 3 cache ran at the same speed as the rest of the CPU?
I'm really not sure how to put this but it doesn't really matter since even thought there more complex parts to the machine building it its all the same. So whether its a larger core or an on-die memory controller as long as the design itself is a good design it won't affect manufacturing.
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Lee XT
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