Originally Posted by danewfie
The only difference between an integrated vs non integrated memory controller is that it is much quicker to talk to memory if its integrated.
AMD processors have a total of 4mbs of combined L2 and L3 cache
Intel Procs have 12
Amd Processors are Native quad cores, and don't use an FSB-type architecture, so all data transfers occur on-die, which reduces latency.
Intel processors are MCMs, and the cores have to (if i remember correctly) send data through the northbridge of the motherboard to be able to talk to each other. <-- slow process
so lets say that, hypothetically the intel's procs perform something like 3 read/write ops per cycle on the L2 cache
Now, as we both know AMD's processors latency between the cores and the cache is drastically lower, lets put their ops/cycle at 9.
See my point?
Now, I know these numbers are made up, so you don't have to call me on it, but they're a fairly accurate representation of the real life workings going on in the procs.
AMD wouldn't consciously put a bottleneck onto their processor cores.... The L2/L3 cache on AMD procs isn't the problem, it's the architecture, but they'll get it figured out soon enough, just wait
I've got my money on the 45nm Phenom X3s... if the 65nm X4 B3's can hit 3.0ghz, then I'm willing to bet that a 45nm part, with one less core will be able to clock much higher due to the lower heat output.
They will be faster than the dual core C2Ds, and probably be priced less too. which is perfect for me