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[TT] First 4GB 1800MHz DDR3 kit released - Page 2

post #11 of 19
I think a bit over 2000 MHz is the record right now. I'm sure we'll see some crazier speeds in the next couple of months.
    
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post #12 of 19
http://www.xtremesystems.org/forums/...d.php?t=177606

Thats the thread related to the current WR for DDR3.. keep in mind this is CAS5 @ 2011mhz

unfortunately there is no everest bandwidth report.. but I guessing its close to 20Gb/s and around 20ns latency.. that is screaming. Just amazing, really.
post #13 of 19
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post #14 of 19
Quote:
Originally Posted by binormalkilla View Post
That may change with Nehalem, considering that the MCH will no longer be in the NB, but rather on the CPU die.
Moving the memory controler to the CPU won't change the value of MHz vs. timings, it will just cut out the middle man. The memory itself will still have the same overall latency.

Quote:
Originally Posted by CL3P20 View Post
http://www.xtremesystems.org/forums/...d.php?t=177606

Thats the thread related to the current WR for DDR3.. keep in mind this is CAS5 @ 2011mhz

unfortunately there is no everest bandwidth report.. but I guessing its close to 20Gb/s and around 20ns latency.. that is screaming. Just amazing, really.
20ns latency is impossible on any current Intel setup.

Chipset latency alone cannot be below 14ns with a tRD (performance level) of 7 on a ~500MHz FSB.

I'd expect around 40ns everest latency.
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post #15 of 19
What would require 20Gb/s RAM apart from stress tests?
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post #16 of 19
20GB/s is unlikely to be possible with current chipsets either. 13-14GB/s is more likely for CL5 DDR3-2000.

Regardless that kind of bandwidth could come in quite handy during multi-tasking. A Quad core cpu can get pretty bandwidth starved when maxed out.
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post #17 of 19
Intel Quickpath Interconnect

Quote:
Performance numbers for QuickPath are reported to be 4.8 to 6.4 Gigatransfers per second (GT/s) per direction, and a link can be 5, 10 or 20 bits wide in each direction. Therefore the bandwidth provided by a full width link amounts to 12.0 to 16.0 GB/s per direction, or 24.0 to 32.0 GB/s per link.[6]

Initial Nehalem Implementation uses a 20-bit wide 25.6 GB/s link (as reported in the Intel Nehalem Speech on IDF). This 25.6 GB/s link provides exactly double the amount of theoretical bandwidth as Intel's FSB 1600 used in the X48 Chipset.
Now one just needs to look for applications that will eat up all of this potential.
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post #18 of 19
Quote:
20ns latency is impossible on any current Intel setup.

Chipset latency alone cannot be below 14ns with a tRD (performance level) of 7 on a ~500MHz FSB.
I'd expect around 40ns everest latency.
Bah.. OK. I got 41ns latency on a 965 chipset, with 1200mhz RAM at cas5... I think 2000mhz and the same cas level, calls for the latency to decrease a little more than 1ns. .. dont you.

Quote:
20GB/s is unlikely to be possible with current chipsets either. 13-14GB/s is more likely for CL5 DDR3-2000.

Regardless that kind of bandwidth could come in quite handy during multi-tasking. A Quad core cpu can get pretty bandwidth starved when maxed out.
Well personally I have achieved over 10k on a bandwidth test, using a set of Crucial Ballistix and a P5B-dlx. Over on XS I have seen a few 15k bandwidth reports... none of which were even close to 2000mhz, cas5. Overall, I might agree with you somewhat, but dont go saying something is impossible.. [after all, current systems are capable of besting 14k/mbs] someone out there will just have to prove you wrong.

*PS, check my photo bucket link for pics of the Everest Bandwidth tests @ 10k mbs.
post #19 of 19
Quote:
Originally Posted by Marin View Post
SO nice.
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