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[Ars] RISC vs. CISC in the Mobile Era

post #1 of 4
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Quote:
Back in 1998, when I first began covering hardware at the newly launched Ars Technica, much of my writing focused on issues raised by the raging Mac vs. PC flame wars that took place in computing forums across the Internet. These flame wars were often centered around the esoteric issue of instruction set architecture (ISA), as partisans on each side argued over which type of ISA was superior—those ISAs based on the RISC philosophy expressed in the PowerPC processors that powered the Mac, or the CISC camp that most think is exemplified by Intel's x86 processors [...]

st-forward to today, and the future of the pocket looks eerily similar to what the future of the desktop looked like from the standpoint of a decade ago. WiMAX and 3G networks are poised to make mobile broadband ubiquitous in large urban centers, and two ISAs, one RISC and one CISC, are poised to do battle yet again on a new terrain that's defined by a shift in how people use their computers.

Unlike 1998, though, RISC vs. CISC actually matters, now. A close look at the design of Intel's newest mobile architecture, officially named Atom, will show why the decades-old "RISC vs. CISC" debate is suddenly interesting again, and in some entirely new ways. In this article, I'll talk about the penalty that Intel's new Atom ultramobile processor pays for its CISC legacy, and how Intel plans to reduce the impact of that penalty with simultaneous multithreading.
Via Ars Technica

This is one of the articles that make Ars stand out for me. It gets more in depth and actually delves into the execution pipeline. They bring up a some good points, especially in relation to how the baggage that x86 brings is hurting Intel in the mobile realm. Makes for a good read

btw for some reason they don't explain RISC/CISC (reduced/complex instruction set computer). Wiki can explain better than I can, but basically RICS processors use an instruction set that contains only simple operations such as an arithmetic calculation, a memory load/store, etc whereas CISC will combine several of these operations into a single instruction. x86 follows the CISC philosophy
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post #2 of 4
the diferences are becoming more and more minimal as more than one of the risc instructions can be done in a single clock.

in the past it might have at times been more effective to do repeated addition for 3 clocks instead of multiplication in 5...
but that doesn't matter when you can do multiplication in 1 clock here and now and just toss that into the RISC instruction set as well...
Edited by xlink - 12/8/10 at 9:55pm
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post #3 of 4
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Originally Posted by xlink View Post
the diferences are becoming more and more minimal as more than one of the risk instructions can be done in a single clock.

in the past it might have at times been more effective to do repeated addition in 3 clocks instead of multiplication in 5...
but that doesn't matter what you can do multiplication in 1 clock here and now and just toss that into the RISC instruction set as well...
That isn't really what the CICS vs RISC issue is. In x86 you have instructions such as

Code:
mov 8(%eax, %ecx, 4), %edx
This translates into move the data stored at address 8+(%eax+4*%ecx) in %edx. This single instruction encodes a multiplication (actually a shift in this case) , two additions, and a memory reference. A large amount of extra hardware is required to decode these complex instructions that are of variable length (that particular instruction has 3 operands and two immediate values whereas a more simple mov could have only two operands and no immediates).

A RISC ISA would require more instructions, but the hardware is much simpler. The article covers this more in depth.

Also, this article is about the mobile space (Atom vs ARM for most of the article) in which the factors which have more or less amortized the cost of a CISC architecture are most definitely not negligible
Edited by rabidgnome229 - 5/19/08 at 4:20pm
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post #4 of 4
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Conclusions

In the near to medium term, Atom and its predecessors will pay a relatively hefty price for their CISC legacy. More benchmarks will give a clearer picture of whether tricks like SMT, when combined with Intel's ongoing process engineering leadership, will lower that price enough to enable x86 to squeeze ARM out of some future version of an iPhone-like device.
iPhones, may be, but other mobile phones where operating systems are built on RISC ISA, no, won't happen.

and benchmarks will not tell us anything at all! because of huge difference in architecture. i got accepted for summer placement in ARM Cambridge for Optimisation on the M3 core. and they told me i will be doing optimisation for a benchmarking code based off Berkeley Design Technology Inc.
benchmarks are all in the optimisation, so im sure Intel is doing it as well.

my opinion is that Atom will win for pure performance and ease of porting x86 instructions onto mobile device, but ARM and other RISC will still dominate the ultra-low powered device, including most mobile phones and most DSP embedded systems. after all, RISC will always be much lower power than CISC will ever be

as xlink said. i was surprised by the amount of stuff ARM code can do when i went to the interview! (didn't know any beforehand) ARM code has 3 operand, so comparing to the usual PIC instructions i learnt, ARM code can do a LOT more in a single instruction.
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