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[EXTREMETECH] PCI Express 3.0 details surface

post #1 of 10
Thread Starter 


Quote:
Here's some good news: when PCI Express 3.0 products launch sometime around the 2010 timeframe, they won't require a new connector.

At a press conference held by the PCI Special Interest Group on Wednesday, SIG chairman Al Yanes briefly outlined the needs for three-slot, 300-watt graphics cards as well as more details on PCI Express 3.0, which executives said last year will transfer information at 8.0 gigatransfers per second.

(The amount of information transferred will depend on how wide the channel is; a x16 channel is the norm today, but the spec allows up to x32 lanes, each transferring 250 Mbytes/s at PCI Express 1.1 speeds and about 500 Mbytes/s at PCI Express 2.0 speeds. At PCI Express 1.1 speeds, thirty-two lanes of 250 MB/s (PCIe 1.1) gives a maximum transfer rate of 8 Gbytes/s, or 16 Gbytes/s at PCI Express 2.0. By removing the requirement for an 8-bit/10-bit encoding scheme found within PCI Express 2.0, PCIe 3.0's 8-gigatransfer/s bit rate effectively delivers double the PCI Express 2.0 bandwidth.)

PCI Express 3.0 will be backwards-compatible with PCI Express 2.0, Yanes said. Since the connector will remain the same, the only difference should be in the electrical specifications. Note that while PCs will only require one connector, servers will still use two PCIe 3.0 connectors, the same as with PCIe 2.0.

While that's the plan, it's not set in stone: the base spec is expeted to be completed in late 2009, while testing is set for a year later, in the second half of 2010. It's unclear how soon after that products will be released.

The other interesting thing was that the SIG has proposed a standard for I/O virtualization, a sticking point in virtualized environments. Basically, what the SIG proposes will work both under a direct connection as well as a fabric-based structure. Address translation is included.
http://www.extremetech.com/article2/...129TX1K0000532
Edited by savagebunny - 6/12/08 at 9:56am
post #2 of 10
Any mentioning of the 10-pin PCIe power plug?
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post #3 of 10
Thread Starter 
This is also kind of with the PCI Express 3.0 detail with a image for 300w three-slot Graphics

http://www.extremetech.com/article2/...2319677,00.asp
post #4 of 10
Quote:
Originally Posted by savagebunny View Post


Here's some good news: when PCI Express 3.0 products launch sometime around the 2010 timeframe, they won't require a new connector.

At a press conference held by the PCI Special Interest Group on Wednesday, SIG chairman Al Yanes briefly outlined the needs for three-slot, 300-watt graphics cards as well as more details on PCI Express 3.0, which executives said last year will transfer information at 8.0 gigatransfers per second.

(The amount of information transferred will depend on how wide the channel is; a x16 channel is the norm today, but the spec allows up to x32 lanes, each transferring 250 Mbytes/s at PCI Express 1.1 speeds and about 500 Mbytes/s at PCI Express 2.0 speeds. At PCI Express 1.1 speeds, thirty-two lanes of 250 MB/s (PCIe 1.1) gives a maximum transfer rate of 8 Gbytes/s, or 16 Gbytes/s at PCI Express 2.0. By removing the requirement for an 8-bit/10-bit encoding scheme found within PCI Express 2.0, PCIe 3.0's 8-gigatransfer/s bit rate effectively delivers double the PCI Express 2.0 bandwidth.)

PCI Express 3.0 will be backwards-compatible with PCI Express 2.0, Yanes said. Since the connector will remain the same, the only difference should be in the electrical specifications. Note that while PCs will only require one connector, servers will still use two PCIe 3.0 connectors, the same as with PCIe 2.0.

While that's the plan, it's not set in stone: the base spec is expeted to be completed in late 2009, while testing is set for a year later, in the second half of 2010. It's unclear how soon after that products will be released.

The other interesting thing was that the SIG has proposed a standard for I/O virtualization, a sticking point in virtualized environments. Basically, what the SIG proposes will work both under a direct connection as well as a fabric-based structure. Address translation is included.

http://www.extremetech.com/article2/...129TX1K0000532
Good, I can be lazy and not post this!

Also, you should put text that isn't yours in quote tags.
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post #5 of 10
Thread Starter 
Done, sorry about that, in the middle of making lunch

but ya, this may require a great deal of power to run, and don't need to get a new mobo over it also, backwards just like with PCI Express 2.0 and x16 boards
post #6 of 10
Woohoo for 3 slot coolers!

if they keep this up we will need E-ATX boards to be able to run crossfire/Sli LOL.
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post #7 of 10
OMG...PCIE 2.0 just came out...3.0 already?!?!?
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post #8 of 10
Quote:
Originally Posted by porky View Post
OMG...PCIE 2.0 just came out...3.0 already?!?!?

"While that's the plan, it's not set in stone: the base spec is expeted to be completed in late 2009, while testing is set for a year later, in the second half of 2010."
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post #9 of 10
yay, thats gonna delay my upgrading plans... not
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post #10 of 10
I read 2010.... So.... divide by half and multiply by 3... Thats the real date to expect!~!
    
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