I'm really disappointed that AMD hasn't mentioned anything about the progress of their ZRAM development, since it is basically the same thing as what Intel is trying to do here and AMD already has the big advantage as it has already been demonstrated on SOI already.
THEREâ€™S A GEEK-FEST TAKING PLACE in Hawaiâ€™i, of all places, and itâ€™s called the VLSI Symposia â€“ thatâ€™s fine by us, give us a working vacation any day overâ€¦uhmâ€¦ work. The crammed brains-in-attendance have been able to show some interesting developments in the field of semiconductor research â€“ including Intelâ€™s own slideware which theyâ€™ve so graciously sent us for analysis.
If youâ€™ve been following Intelâ€™s achievements over the past few years, youâ€™ll have noticed that Chipzilla is they are repeatedly reaching the design limit on a few elements in their chips. The latest example had been the leaky 45nm process, which they bathed in Hafnium and gave high-K metal gates. Now Intel is trying to push cache to a guesstimated 3 to 4 times its current capacity by using Floating Body Cells (FBC).
Floating Body Cells have nothing to do with corpses bobbing up and down in the Hudson River. Itâ€™s all about SOI, and although Intel didnâ€™t like IBM/AMDâ€™s SOI back in the daze they like it enough now that they need it. The FBC (your bit of storage) hangs under the gate and over the 10nm thin buried oxide (BOX) layer, meaning its small, simple (ie: cost effective) and â€“ from what we garner, wonâ€™t suffer from the electric shortcomings of current DRAM designs. Intel also says itâ€™s a bit more scalable than previous caches. This would also, potentially, lead to a new species of DRAM some time down the line, but Intelâ€™s business isnâ€™t about building DRAM, itâ€™s about building CPUs.
Intel is plugging this as the next-gen of cache, with lower costs and higher density. The technology itself has been discussed and worked on by other companies for a few years now (the oldest we can remember was Tosh presenting the same FBC tech, albeit with fewer refinements, at VLSI 2003).
One of the missionaries also presented (what we expect to be) the next transistor technology: High-K + Metal Gate strain-enhanced. Intel is counting on this tech to improve yields and shave some costs off CPU production â€“ an all-round win-win situation, we guess.
Unfortunately the above techs are still a work-in-progress, and Intel didnâ€™t talk timelines â€“ the slideware, however, does say that FBC is suitable for â€œ15nm node and beyondâ€ (about 3-4 years in our calendar) and High K+strained metal gate is the â€œbest transistor results for any published 45nm or 32nm technology" , which sounds like right aboutâ€¦ uhmmâ€¦ now? So you'd expect the Nehalem family to feature this tech as it launches.
For some reason (we canâ€™t imagine which) the Intel missionaries tried to convert the native (and non-native) Hawaiians to the greatness of Nehalemâ€™s clocks â€“ on the argument that decoupling all the clocks and power settings (which for some reason *sounds* wrong to overclockers) is the way to go, hence Quick Path Interconnect.
Unfortunately they were all on Luau time and couldnâ€™t care less. Âµ