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[TPU] Intel Bloomfield 2.66 GHz: First Comprehensive Evaluation BBEENNCCHHIESSS!!! - Page 3

post #21 of 27
Quote:
Originally Posted by Ravin View Post
30% gain clock for clock would likely be Intel's target.....16ops per clock vs. 12 with C2D/Q. Not the revolution from P4 to Core gave us with a 100% gain, but still quite an achievment. Not only are we seeing an increase in ops/clock with Nehalem, we're also going to see an evolution in memory bandwidth available. So far all the benchies are in DUAL CHANNEL DDR3, Nehalem is going to support TRI CHANNEL.

Lest we forget our lessons with Penryn and Wolfdale- the 45nm process has shown to OC very well with low TDP, although they are somewhat voltage sensitive. The "Tick" of Nehalem will be interesting indeed....Hopefully "Tock" die-shrink to 32nm fares as well as the 90nm--->65nm shrink did.
Please don't bring back that 6,9,12,16 operations per clock crap back. It was so hard smashing that myth.
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post #22 of 27
Quote:
Originally Posted by pauldovi View Post
Please don't bring back that 6,9,12,16 operations per clock crap back. It was so hard smashing that myth.
Its a myth? lol...
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post #23 of 27
Quote:
Originally Posted by Somenoob View Post
Its a myth? lol...
Yeah... It is a lot more complicated than that!
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post #24 of 27
Quote:
Originally Posted by YeaBaby View Post
Hey I have no doubt Nehalem is going to PWN!! One thing you left out is the return of hyper threading so a 4 core Nehalem will be able to execute 8 threads at a time. I doubt that tri channel vs. dual channel will make much of a difference but I could be wrong. Anyways the early LGA 1360 parts will be tri channel and the Q3 2009 parts on LGA 1160 will still be dual channel.
I'm taking the return of HT with a grain of NaCl. It wasn't so hot the first time around, but in theory it's a good idea.

Quote:
Originally Posted by pauldovi View Post
Yeah... It is a lot more complicated than that!
It's not a myth, but you are right it is more complicated than just a simple op/ck number- which is only meant to be a rough measure of the sum of how the archetecture handles executions. It's a theoretical vs. real world scenario, but the rough ratios actually do apply. Not everyone here knows how to interpret instruction sets and pipeline stages- which boil down to your op/ck...layman OCer term.
Edited by Ravin - 7/9/08 at 9:11pm
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post #25 of 27
I think people should be impressed by these results. Many were expecting the same jump as p4 to conroe gave, but that's just not possible. The P4->conroe jump was from a bad architecture to a good one. This new jump is from a good architecture to a better one.

We're still getting 30% increases clock for clock, as well as a simplified data bus that gives MASSIVE gains on memory bandwidth, as well as better scaling on multiple cores.
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post #26 of 27
Quote:
Originally Posted by pauldovi View Post
Yeah... It is a lot more complicated than that!
Quote:
Originally Posted by Ravin View Post
It's not a myth, but you are right it is more complicated than just a simple op/ck number- which is only meant to be a rough measure of the sum of how the archetecture handles executions. It's a theoretical vs. real world scenario, but the rough ratios actually do apply. Not everyone here knows how to interpret instruction sets and pipeline stages- which boil down to your op/ck...layman OCer term.
I'm still confused, is it a myth or not?!
post #27 of 27
eep! it'll squish me! but i'll like it...
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