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[THG] 'Nehalem' 2.93 GHz Benches Revealed - Page 2

post #11 of 39
Quote:
Originally Posted by pauldovi View Post
The first one compared Nehalem to X6800 the second Nehalem to QX6800. Whats your point?
I didn't read the article that closely, but if in fact they did compare an 4 core 8 thread Nehalem to a 4 core 4 thread Conroe and the Nehalem only beats it by 4% that would seem to indicate Nehalem as a massive PHAIL. Thats his point. Can anyone say Conroe with a nothbridge glued onto it. yawn.
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post #12 of 39
Nehalem improvements will primarily be a result of the IMC, interconnects, and instruction extensions. I called this a million years ago. There will be virtually no IPC improvements. DO NOT EXPECT ANOTHER P4 -> CONROE style leap.

Intel's ticker is busted.

^^ I like that line, quick somebody quote it.

    
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post #13 of 39
Quote:
Originally Posted by pauldovi View Post
The first one compared Nehalem to X6800 the second Nehalem to QX6800. Whats your point?

The test is weird, I mean FX-62? FX74? x6800... I'm not used to seeing this kind of numbers.
Edited by dragosmp - 7/9/08 at 11:34pm
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post #14 of 39
Quote:
Originally Posted by RonindeBeatrice View Post
Nehalem improvements will primarily be a result of the IMC, interconnects, and instruction extensions. I called this a million years ago. There will be virtually no IPC improvements. DO NOT EXPECT ANOTHER P4 -> CONROE style leap.

Intel's ticker is busted.

^^ I like that line, quick somebody quote it.


No thanks because that isnt true.

We'll have to see what AMD has to offer agaist nehalem for my next upgrade
    
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post #15 of 39
Quote:
Originally Posted by arkheii View Post
Sensationalism? Remember though that they're using PC Mark 05, which is an old benchmark that probably isn't optimized to reflect any advantages the Nehalem could have.
I totally agree with you

Not to mention that PCMark 05 is just a synthetic benchmark, that doesn't reflect the real world performance

Moreover, anandtech had benchmarked Nehalem 2.66GHz and it seems that there were huge performance improvement over Yorkfield in some real world applications

http://www.anandtech.com/cpuchipsets...spx?i=3326&p=6
Edited by TheWay - 7/10/08 at 1:06am
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post #16 of 39
Quote:
Originally Posted by pauldovi View Post
The first one compared Nehalem to X6800 the second Nehalem to QX6800. Whats your point?
That they're still using inaccurate numbers to inflate the difference between the architectures.
post #17 of 39
Quote:
Originally Posted by darkcloud89 View Post
That they're still using inaccurate numbers to inflate the difference between the architectures.
You are getting upset because a X6800 scores differently than a QX6800. That not inflating anything, they are different processor!

The other benchmark cannot really be used. Who knows if the two tests used the same hardware / OS / drivers as the first test?
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post #18 of 39
My question is how does this reconcile with the results obtained by Anandtech in their "Intel does it Again" article?
http://www.anandtech.com/showdoc.aspx?i=3326&p=9
Edited by Urufu_Shinjiro - 7/10/08 at 7:34am
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post #19 of 39
Where you are really going to see the difference is in greater than 2 processor socket systems. Compare a 4s conroe xeon to 4s nahalem and you will see a world of difference in throughput.
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post #20 of 39
Quote:
Originally Posted by RonindeBeatrice View Post
Nehalem improvements will primarily be a result of the IMC, interconnects, and instruction extensions. I called this a million years ago. There will be virtually no IPC improvements. DO NOT EXPECT ANOTHER P4 -> CONROE style leap.

Intel's ticker is busted.

^^ I like that line, quick somebody quote it.

Something many people overlook is the increase in clock frequency of Core 3. Core 3 also features several significant improvements that are more than just "instruction extensions".

Quote:
Originally Posted by pauldovi
  • Nehalem is a modular architecture supporting integrated graphics and I/O chips
  • 33% more in-flight micro-ops than Core. What does this mean:
Quote:
Nehalem allows for 33% more micro-ops in flight compared to Penryn (128 micro-ops vs. 96 in Penryn), this increase was achieved by simply increasing the size of the re-order window and other such buffers throughout the pipeline.

With more micro-ops in flight, Nehalem can extract greater instruction level parallelism (ILP) as well as support an increase in micro-ops thanks to each core now handling micro-ops from two threads at once.
  • Improvements in unaligned cache access performance. What does this mean:
Quote:
In SSE there are two types of instructions: one if your data is aligned to a 16-byte cache boundary, and one if your data is unaligned. In current Core 2 based processors, the aligned instructions could execute faster than the unaligned instructions. Every now and then a compiler would produce code that used an unaligned instruction on data that was aligned with a cache boundary, resulting in a performance penalty. Nehalem fixes this case (through some circuit tricks) where unaligned instructions running on aligned data are now fast.

  • New second level brand predictor per core. What does this mean:
Quote:
Nehalem also introduces a second level branch predictor per core. This new branch predictor augments the normal one that sits in the processor pipeline and aids it much like a L2 cache works with a L1 cache. The second level predictor has a much larger set of history data it can use to predict branches, but since its branch history table is much larger, this predictor is much slower. The first level predictor works as it always has, predicting branches as best as it can, but simultaneously the new second level predictor will also be evaluating branches. There may be cases where the first level predictor makes a prediction based on the type of branch but doesn't really have the historical data to make a highly accurate prediction, but the second level predictor can. Since it (the 2nd level predictor) has a larger history window to predict from, it has higher accuracy and can, on the fly, help catch mispredicts and correct them before a significant penalty is incurred.
  • New L2 and L3 memory system (doesn't just help scaling!)
According to Wikipedia:


  • 1.1x to 1.25x the single-threaded performance or 1.2x to 2x the multithreaded performance at the same power level
  • 30% lower power usage for the same performance
  • According to a preview from AnandTech "expect a 20 - 30% overall advantage over Penryn with only a 10% increase in power usage. It looks like Intel is on track to delivering just that in Q4."
Sources:


http://en.wikipedia.org/wiki/Nehalem_(microarchitecture)
http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3264

So you are very correct that Nehalem looks to vastly improve on its scalability, something that has been needed desperately, you assume that this is the only changes and that these changes only affect multi-CPU environments.
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