1. FSB Strap to North Bridge - higer strap will be more stable (and give you more mem dividers) - but the NB timeings will be looser.
2.DRAM Static Read Control - disable
3.DRAM Read Training - disable
4.MEM. OC Charger - enabled
5.Ai Clock Twister -Auto
6.Ai Transaction Booster - Auto
7.CPU Spread Spectrum - disable
8. PCIE Spread Spectrum - disable
9. CPU Clock Skew -Auto
10. NB Clock Skew - Auto
11.CPU Margin Enhancement - No Idea



EDIT: bios pics show CPU and NB Clock Skew as Normal - I now have this set to AUTO
Edited by Ando - 1/21/09 at 3:37pm
2.DRAM Static Read Control - disable
3.DRAM Read Training - disable
4.MEM. OC Charger - enabled
5.Ai Clock Twister -Auto
6.Ai Transaction Booster - Auto
7.CPU Spread Spectrum - disable
8. PCIE Spread Spectrum - disable
9. CPU Clock Skew -Auto
10. NB Clock Skew - Auto
11.CPU Margin Enhancement - No Idea



EDIT: bios pics show CPU and NB Clock Skew as Normal - I now have this set to AUTO
Edited by Ando - 1/21/09 at 3:37pm




The solution is said to be 'enable Load Line Calibration", which you have, but I don't. Where it is with you, there is nothing with me. In fact, I also don't have the PCIE Sata and CPU PLL voltage settings.

