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post #1421 of 6378
Quote:
Originally Posted by buffalofloyd View Post
I have the same memory as you and I have seen that first BSOD more times than I care to remember. I don't know much about this overclocking stuff so trying to lower the timings of my RAM has been a nightmare. I have resorted to leaving the timings on auto with a QPI/DRAM of 1.26875. This sets my timings to 9-9-9-24 and I seem to be fairly stable. I don't know how to get them any lower than that. I have been able to leave the voltage at 1.26875 and manually set the timings to 8-8-8-24 with limited success. Prime95 runs fine and so does OCCT but I fail the IBT and LinX. I'm sure somebody with more knowledge could get my timings lower. I don't know if any of this helps or not.
Try upping QPI/DRAM to 1.27500.
I have found this to be a sweet spot for my rig which allowed me for low volts on core & DRAM as well as better timings.

Whenever I would try to get even a step lower - IBT fails same like for you.

If this won't help, post your other settings so we can have a look.
    
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post #1422 of 6378
QPI/DRAM seems to be the issue for you, trying just uping it until stable or until you reach 1.4 then try something else...
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post #1423 of 6378
I dont know if this is right place, but has anybody had issues installing a
Thermalright Ultra Extreme 120 Rev C heatsink (with newer boltthru kit)? I can't seem to have a secure mount between the backplate and mobo nor can I install the heatsink (spring screws dont seem to wanna screw in, almost like they're too short). Any help is much appreciated.
post #1424 of 6378
After some overclock on my 930 with those settings :

Code:
Ai Overclock Tuner.....................[Manual]
CPU Ratio Setting......................[21.0]
Intel(r) SpeedStep(tm) Tech............[Disabled]
Xtreme Phase Full Power Mode...........[Enabled]
BCLK Frequency.........................[191]
PCIE Frequency.........................[100]
DRAM Frequency.........................[DDR3-1531MHz]
UCLK Frequency.........................[Auto]
QPI Link Data Rate.....................[Auto]

CPU Voltage Control....................[Manual]
CPU Voltage............................[1.2875]
CPU PLL Voltage........................[Auto]
QPI/DRAM Core Voltage..................[1.25]
IOH Voltage............................[Auto]
IOH PCIE Voltage.......................[Auto]
ICH Voltage............................[Auto]
ICH PCIE Voltage.......................[Auto]
DRAM Bus Voltage.......................[1.64]
DRAM DATA REF Voltage on CHA...........[Auto]
DRAM CTRL REF Voltage on CHA...........[Auto]
DRAM DATA REF Voltage on CHB...........[Auto]
DRAM CTRL REF Voltage on CHB...........[Auto]
DRAM DATA REF Voltage on CHC...........[Auto]
DRAM CTRL REF Voltage on CHC...........[Auto]

Load-Line Calibration..................[Enabled]
CPU Differential Amplitude.............[Auto]
CPU Clock Skew.........................[Auto]
CPU Spread Spectrum....................[Disabled]
IOH Clock Skew.........................[Auto]
PCIE Spread Spectrum...................[Disabled]

C1E Support............................[Disabled]
Hardware Prefetcher....................[Enabled]
Adjacent Cache Line Prefetch...........[Enabled]
Intel(r) Virtualization Tech...........[Disabled]
CPU TM Function........................[Enabled]
Execute Disable Bit....................[Enabled]
Intel(r) HT Technology.................[Enabled]
Active Processor Cores.................[All]
A20M...................................[Disabled]
Intel(r) SpeedStep(tm) Tech............[Disabled]
Intel(r) C-STATE Tech..................[Disabled]
Do you think i need to enabled both Spectrum / C1E / Intel(r) SpeedStep(tm) Tech ?

I know it's some kind of power managment have any others information?
post #1425 of 6378
Quote:
Originally Posted by kizzo View Post
After some overclock on my 930 with those settings :

Do you think i need to enabled both Spectrum / C1E / Intel(r) SpeedStep(tm) Tech ?

I know it's some kind of power managment have any others information?
Leave Spectrum Disabled.
Enable C1E & SpeedStep, will save you some juice and lower temps on idle.
I've had to disable C1E but only because my mobo gives noise when volts jumps ~1.1-1.2v

However, as for the Load Line Calibration, I would rather set value than leave on auto. When I've experimented with it, a set value was more stable and allowed lower voltage on core than Auto.
    
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post #1426 of 6378
Bad news for me, my C7D ram doesn't boot anymore with CL6@1.5v
Thought it is volts at first but, not, only latencies, when changed to CL7, no problems.

Some heads up of possible things to come for other runnings these speeds on this RAM.

On another note, interesting article appeared on the Anand about SATA 3 + X58 (and others), however I was disappointed not to find tests on our mobo.

Just to make sure I've checked back Everest to make sure and Marvell on our boards sits on PCIe 2.0 x2 lane which gives 2GB/s so more than enough for 750MB/s which SATA 3 needs.

Another PCIe 2.0 x2 IOH lane goes to USB 3.0 - that's with remaining lanes occupied by x2 SLI in 16 + 16 or tri in 16 + 8 + 8, so there will be never bandwidth problems.

The only thing which I'm not sure now is how the 16 + 16 + 1 mode works.
How comes 33 lanes fits in 32 I have no idea

BTW - can't wait remaining hours till Fermi release
    
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post #1427 of 6378
I was never able to run my at 6-7-6, at least at 1.5-1.64v. It would boot but gave early LinX errors.

Still working great with 1.5v @ C7. My CPU seems to be needing a little higher Vcore than it used though...


Quote:
Originally Posted by luke997 View Post
Bad news for me, my C7D ram doesn't boot anymore with CL6@1.5v
Thought it is volts at first but, not, only latencies, when changed to CL7, no problems.

Some heads up of possible things to come for other runnings these speeds on this RAM.

On another note, interesting article appeared on the Anand about SATA 3 + X58 (and others), however I was disappointed not to find tests on our mobo.

Just to make sure I've checked back Everest to make sure and Marvell on our boards sits on PCIe 2.0 x2 lane which gives 2GB/s so more than enough for 750MB/s which SATA 3 needs.

Another PCIe 2.0 x2 IOH lane goes to USB 3.0 - that's with remaining lanes occupied by x2 SLI in 16 + 16 or tri in 16 + 8 + 8, so there will be never bandwidth problems.

The only thing which I'm not sure now is how the 16 + 16 + 1 mode works.
How comes 33 lanes fits in 32 I have no idea

BTW - can't wait remaining hours till Fermi release
post #1428 of 6378
Quote:
Originally Posted by ekovalsky View Post
I was never able to run my at 6-7-6, at least at 1.5-1.64v. It would boot but gave early LinX errors.

Still working great with 1.5v @ C7. My CPU seems to be needing a little higher Vcore than it used though...
Intersting... so it seems like mem and cpu degrades quite quickly...
    
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post #1429 of 6378
Quote:
Originally Posted by buffalofloyd View Post
I have the same memory as you and I have seen that first BSOD more times than I care to remember. I don't know much about this overclocking stuff so trying to lower the timings of my RAM has been a nightmare. I have resorted to leaving the timings on auto with a QPI/DRAM of 1.26875. This sets my timings to 9-9-9-24 and I seem to be fairly stable. I don't know how to get them any lower than that. I have been able to leave the voltage at 1.26875 and manually set the timings to 8-8-8-24 with limited success. Prime95 runs fine and so does OCCT but I fail the IBT and LinX. I'm sure somebody with more knowledge could get my timings lower. I don't know if any of this helps or not.
I believe this can be fixed by adjusting the Phase Locked Loop voltages. Whether you need higher or lower value, I cannot say as all CPUs vary as well as motherboard quality may vary from one to another even if it is the same model. Let me explain.

The operation of a phase locked loop, PLL, is based around the idea of comparing the phase of two signals. This information about the error in phase or the phase difference between the two signals is then used to control the frequency of the loop.

To understand more about the concept of phase and phase difference, first visualise a radio frequency signal in the form of a familiar x-y plot of a sine wave. As time progresses the amplitude oscillates above and below the line, repeating itself after each cycle. The linear plot can also be represented in the form of a circle. The beginning of the cycle can be represented as a particular point on the circle and as a time progresses the point on the waveform moves around the circle. Thus a complete cycle is equivalent to 360 degrees. The instantaneous position on the circle represents the phase at that given moment relative to the beginning of the cycle.

To look at the concept of phase difference, take the example of two signals. Although the two signals have the same frequency, the peaks and troughs do not occur in the same place. There is said to be a phase difference between the two signals. This phase difference is measured as the angle between them. It can be seen that it is the angle between the same point on the two waveforms. In this case a zero crossing point has been taken, but any point will suffice provided that it is the same on both.

When there two signals have different frequencies it is found that the phase difference between the two signals is always varying. The reason for this is that the time for each cycle is different and accordingly they are moving around the circle at different rates. It can be inferred from this that the definition of two signals having exactly the same frequency is that the phase difference between them is constant. There may be a phase difference between the two signals. This only means that they do not reach the same point on the waveform at the same time. If the phase difference is fixed it means that one is lagging behind or leading the other signal by the same amount, i.e. they are on the same frequency.

. A phase-locked loop is used to set a frequency in such a manner that it matches a reference frequency produced by a reference oscillator. The match must be so accurate that the phase shift between the two frequencies does not drift. Phase locked loops (PLLs) are utilized by electronic devices to generate clock signals from a reference signal. The generated clock signal may be at the same frequency as the reference clock signal or at a fractional or multiple frequency of the reference clock signal. The generated clock signal typically has a predetermined phase relationship with the reference clock signal. Phase-locked loop (PLL) integrated circuits produce an oscillator frequency output which matches an input frequency signal. A typical PLL may include a phase-frequency detector, a charge pump, and a voltage-controlled oscillator (VCO). A phase locked loop circuit operates by producing an oscillator frequency to match the frequency of an input signal. The phase frequency detector compares an input or system clock with an output clock and provides clock control signals to the charge pump. The charge pump adds or subtracts charge to a filter capacitor based on the clock control signals and generates a control voltage that controls the frequency of the VCO. Another block may be provided to buffer and divide or multiply the output clock, which is fed back to the PFD for comparison with the system clock. Phase-locked loops are widely used in digital electronics, signal telemetry, and communications applications. Phase Locked Loop (PLL) circuits may be used for frequency control. Many applications require phase-locked loop (PLL) circuits which will work with high frequencies. PLL circuits may be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits.
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post #1430 of 6378
Quote:
Originally Posted by luke997 View Post
Leave Spectrum Disabled.
Enable C1E & SpeedStep, will save you some juice and lower temps on idle.
I've had to disable C1E but only because my mobo gives noise when volts jumps ~1.1-1.2v

However, as for the Load Line Calibration, I would rather set value than leave on auto. When I've experimented with it, a set value was more stable and allowed lower voltage on core than Auto.
Thanks for your answer !

What do you mean by "i would rather set value" for Load line calibration i only have Disabled / enabled / and Auto ... maybe is linked with something else.
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