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# [Official] --The Asus P6X58D Premium & E Thread-- - Page 144

Quote:
 Originally Posted by 88EVGAFTW I believe this can be fixed by adjusting the Phase Locked Loop voltages. Whether you need higher or lower value, I cannot say as all CPUs vary as well as motherboard quality may vary from one to another even if it is the same model. Let me explain. The operation of a phase locked loop, PLL, is based around the idea of comparing the phase of two signals. This information about the error in phase or the phase difference between the two signals is then used to control the frequency of the loop. To understand more about the concept of phase and phase difference, first visualise a radio frequency signal in the form of a familiar x-y plot of a sine wave. As time progresses the amplitude oscillates above and below the line, repeating itself after each cycle. The linear plot can also be represented in the form of a circle. The beginning of the cycle can be represented as a particular point on the circle and as a time progresses the point on the waveform moves around the circle. Thus a complete cycle is equivalent to 360 degrees. The instantaneous position on the circle represents the phase at that given moment relative to the beginning of the cycle. To look at the concept of phase difference, take the example of two signals. Although the two signals have the same frequency, the peaks and troughs do not occur in the same place. There is said to be a phase difference between the two signals. This phase difference is measured as the angle between them. It can be seen that it is the angle between the same point on the two waveforms. In this case a zero crossing point has been taken, but any point will suffice provided that it is the same on both. When there two signals have different frequencies it is found that the phase difference between the two signals is always varying. The reason for this is that the time for each cycle is different and accordingly they are moving around the circle at different rates. It can be inferred from this that the definition of two signals having exactly the same frequency is that the phase difference between them is constant. There may be a phase difference between the two signals. This only means that they do not reach the same point on the waveform at the same time. If the phase difference is fixed it means that one is lagging behind or leading the other signal by the same amount, i.e. they are on the same frequency. . A phase-locked loop is used to set a frequency in such a manner that it matches a reference frequency produced by a reference oscillator. The match must be so accurate that the phase shift between the two frequencies does not drift. Phase locked loops (PLLs) are utilized by electronic devices to generate clock signals from a reference signal. The generated clock signal may be at the same frequency as the reference clock signal or at a fractional or multiple frequency of the reference clock signal. The generated clock signal typically has a predetermined phase relationship with the reference clock signal. Phase-locked loop (PLL) integrated circuits produce an oscillator frequency output which matches an input frequency signal. A typical PLL may include a phase-frequency detector, a charge pump, and a voltage-controlled oscillator (VCO). A phase locked loop circuit operates by producing an oscillator frequency to match the frequency of an input signal. The phase frequency detector compares an input or system clock with an output clock and provides clock control signals to the charge pump. The charge pump adds or subtracts charge to a filter capacitor based on the clock control signals and generates a control voltage that controls the frequency of the VCO. Another block may be provided to buffer and divide or multiply the output clock, which is fed back to the PFD for comparison with the system clock. Phase-locked loops are widely used in digital electronics, signal telemetry, and communications applications. Phase Locked Loop (PLL) circuits may be used for frequency control. Many applications require phase-locked loop (PLL) circuits which will work with high frequencies. PLL circuits may be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits.
It's official... my brain just exploded Not to sound ungrateful but what you are explaining here is just a tad bit beyond my comprehension. Most of the stuff in the BIOS settings is as well. I feel rather fortunate to have gotten this machine up and running having never built a computer before in my life. I have a semi-successful overclock right now thanks to xmisery's settings he provided on page 1 of this thread.

I would love to get my RAM timings faster if it would increase performance but from what a few on here have told me the difference is minimal. Not like the big wow factor of overclocking your CPU for example. Whether this is true or not I cannot say. I have had lots of trouble with BSOD prolly cause I don't really know what I'm doing but I have not got any recently leaving my RAM settings on auto and the DRAM voltage at 1.26875. I think my computer is running pretty fast. Really fast compared to my previous Pentium D I had. I plan to tinker around more with my system when I understand more about what I'm actually tinkering with. I don't want to damage anything and with my luck I probably would. Thanks for your insight though and when I get more of a clue about this I will re-read what you wrote. As of right now it's sounds like Chinese to me

Cheers,
Jim
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Quote:
 Originally Posted by kizzo Thanks for your answer ! What do you mean by "i would rather set value" for Load line calibration i only have Disabled / enabled / and Auto ... maybe is linked with something else.
By that I meant to set the amplitude ( next field) to a set value, i.e. 700mv (and, obviously LLC to enable).
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Quote:
 Originally Posted by 88EVGAFTW I believe this can be fixed by adjusting the Phase Locked Loop voltages. Whether you need higher or lower value, I cannot say as all CPUs vary as well as motherboard quality may vary from one to another even if it is the same model. Let me explain. The operation of a phase locked loop, PLL, is based around the idea of comparing the phase of two signals. This information about the error in phase or the phase difference between the two signals is then used to control the frequency of the loop. [...]
Thanks for a very interesting reading, +1 rep
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I think that is beyond everyones comprehension All in all, PLL just prevents frequency jitter (cleans up the signals and frequencies) some cpu/mainboard combinations may need higher or lower than stock PLL Voltages.

A typical specifcation is that the maximum jitter be less than 250ps (pico seconds) peak to peak. Since the output of the PLL is not accessible it is important that the system clock input meet this specification.

A divide counter (M) is inserted in the feedback loop to increase the VCO frequency above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (FFB) applied to one input of the PFD is locked to the FREF that is applied to the other input of the PFD. The VCO output feeds post-scale counters which allow a number of harmonically related frequencies to be produced within the PLL.

The output frequency of the PLL is equal to the VCO frequency (FVCO) divided by the post-scale counter (C).

In the form of equations:

*
FREF = FIN / N
*
FVCO = FREF Ã— M = FIN Ã— M/N
* FOUT = FVCO / C = (FREF Ã— M) / C = (FIN Ã— M) / (N Ã— C)

where:

* FVCO = VCO frequency
* FIN = input frequency
* FREF = reference frequency
* FOUT = output frequency
* M = counter (multiplier), part of the clock feedback path
* N = counter (divider), part of the input clock reference path
* C = post-scale counter (divider)
Edited by 88EVGAFTW - 3/26/10 at 2:39am
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Quote:
 Originally Posted by 88EVGAFTW * FREF = FIN / N * FVCO = FREF Ã— M = FIN Ã— M/N * FOUT = FVCO / C = (FREF Ã— M) / C = (FIN Ã— M) / (N Ã— C)
Those formulas really helped me out.

I was having some trouble on my DFI UT X58-T3eH8 stabilizing the clocks, but adjusting the PLL with your help really fixed the problem.
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Quote:
 Originally Posted by luke997 By that I meant to set the amplitude ( next field) to a set value, i.e. 700mv (and, obviously LLC to enable).
Thanks a lot !

Any other advise ?
I certainly don't want to start a flame war or fanboy war in this thread. I am no fanboy. But with all the crap NVIDIA has pulled lately, I enjoyed selling my 285 GTX's and giving NVIDIA a huge middle finger with my package arrival yesterday

Now I just need another one
Nice! Although i have never been a fan of ATI.
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Quote:
 Originally Posted by BlackDragon24 I certainly don't want to start a flame war or fanboy war in this thread. I am no fanboy. But with all the crap NVIDIA has pulled lately, I enjoyed selling my 285 GTX's and giving NVIDIA a huge middle finger with my package arrival yesterday Now I just need another one
Very nice score, 4K more on GPU than mine 295!

I have nothing against both makers but as 3D user I have just one option...
Perhaps in 18-24 months there will be some good driver/games for ATI too so there would be a choice.

Your's memory keeping well?
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Quote:
 Originally Posted by luke997 Very nice score, 4K more on GPU than mine 295! I have nothing against both makers but as 3D user I have just one option... Perhaps in 18-24 months there will be some good driver/games for ATI too so there would be a choice. Your's memory keeping well?
Yes it is. I saw that it is no longer a go at Cas6 for you, which is strange to say the least. I've taken mine up to 1640 6-7-6-18-1T 1.5v with no problems. But if it doesn't boot one morning I guess I'll know what to look for first.

One thing I can say for sure about the 5970 over the 285's in SLI is image quality. It was almost like going from a regular tube tv to high def. Even my wife commented on how much crisper things looked in the games she plays. Hey if the wife is happy with the \$600 video card then I guess that's a win
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