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Core Architecture Announced – Features a Plenty

post #1 of 3
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Quote:
At today’s Intel Developer Forum keynote, Intel’s CTO Justin Rattner announced that the Core architecture has four issue execution with a fourteen stage pipeline. Rattner focused on five new technologies that will make Core different than previous architectures like Netburst. The wider issue execution was obviously the first and most important announcement. However, Conroe will also feature a new 128-bit SSE optimization that will allow all SSE instructions to be completed in a single cycle.
http://dailytech.com/article.aspx?newsid=1146

Hmm. If I read this correct, Conroe only does 4 ops/clock...
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post #2 of 3
I have to say good job on these finds mate..And Conroe is going to kick ass
post #3 of 3
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Originally Posted by ENTERPRISE1701
I have to say good job on these finds mate..And Conroe is going to kick ass
Yeah!!! , BTW Nice finds pauldovi
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