i5 760 noob overclocking :)

why are you stopping at 3.6?? Also please fill this in:
http://www.overclock.net/specs.php

Don't forget to brush up on Phase Locked Loops to further understand problems that may arise at higher clocks.

Here is some more info on the Phase Locked Loop voltages. Whether you need higher or lower value, I cannot say as all CPUs vary as well as motherboard quality may vary from one to another even if it is the same model. Let me explain.

The operation of a phase locked loop, PLL, is based around the idea of comparing the phase of two signals. This information about the error in phase or the phase difference between the two signals is then used to control the frequency of the loop.

To understand more about the concept of phase and phase difference, first visualise a radio frequency signal in the form of a familiar x-y plot of a sine wave. As time progresses the amplitude oscillates above and below the line, repeating itself after each cycle. The linear plot can also be represented in the form of a circle. The beginning of the cycle can be represented as a particular point on the circle and as a time progresses the point on the waveform moves around the circle. Thus a complete cycle is equivalent to 360 degrees. The instantaneous position on the circle represents the phase at that given moment relative to the beginning of the cycle.

To look at the concept of phase difference, take the example of two signals. Although the two signals have the same frequency, the peaks and troughs do not occur in the same place. There is said to be a phase difference between the two signals. This phase difference is measured as the angle between them. It can be seen that it is the angle between the same point on the two waveforms. In this case a zero crossing point has been taken, but any point will suffice provided that it is the same on both.

When there two signals have different frequencies it is found that the phase difference between the two signals is always varying. The reason for this is that the time for each cycle is different and accordingly they are moving around the circle at different rates. It can be inferred from this that the definition of two signals having exactly the same frequency is that the phase difference between them is constant. There may be a phase difference between the two signals. This only means that they do not reach the same point on the waveform at the same time. If the phase difference is fixed it means that one is lagging behind or leading the other signal by the same amount, i.e. they are on the same frequency.

A phase-locked loop is used to set a frequency in such a manner that it matches a reference frequency produced by a reference oscillator. The match must be so accurate that the phase shift between the two frequencies does not drift. Phase locked loops (PLLs) are utilized by electronic devices to generate clock signals from a reference signal. The generated clock signal may be at the same frequency as the reference clock signal or at a fractional or multiple frequency of the reference clock signal. The generated clock signal typically has a predetermined phase relationship with the reference clock signal. Phase-locked loop (PLL) integrated circuits produce an oscillator frequency output which matches an input frequency signal. A typical PLL may include a phase-frequency detector, a charge pump, and a voltage-controlled oscillator (VCO). A phase locked loop circuit operates by producing an oscillator frequency to match the frequency of an input signal. The phase frequency detector compares an input or system clock with an output clock and provides clock control signals to the charge pump. The charge pump adds or subtracts charge to a filter capacitor based on the clock control signals and generates a control voltage that controls the frequency of the VCO. Another block may be provided to buffer and divide or multiply the output clock, which is fed back to the PFD for comparison with the system clock. Phase-locked loops are widely used in digital electronics, signal telemetry, and communications applications. Phase Locked Loop (PLL) circuits may be used for frequency control. Many applications require phase-locked loop (PLL) circuits which will work with high frequencies. PLL circuits may be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits.

tl;dr - adjusting PLL voltages will help keep sin waves in sync of the actual clocks and the clock generator.

Your CPU temp is probably a few *c lower than core temp, so don't worry too much (i think? idk). Also, how can you get such poor temps with a D14? Are you only using 1 fan?.. try reseating/reapplying TIM if you get bad temps.