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post #9671 of 10523
Quote:
Originally Posted by TheBlademaster01 View Post

About the latch:

http://www.techpowerup.com/forums/showpost.php?p=2775935&postcount=94

i was gonna say something, but I think i'm late to my own party.
 
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post #9672 of 10523
Quote:
Originally Posted by mmonnin View Post

Theres probably no Si exposed, IHS or not. At least all memory is packaged and is what you see soldered to the stick or chip. Si would be more like the bright rainbow color you see when Intel announces new process node and they hold up a wafer. SI oxidizes anyway, which would be horrible for thermal transfer.
I've seen a few Duron/Athlon CPUs chipped before and still work. Si was never exposed, just the packaging on top.

That's because the polysilicon material is not on top of the die. First you have the molded layer, then the metal wires, gating material, insulators and inside are the active polysilicon regions. Even so, you can scratch through the thin layer on top of the die and damage the chip pretty easily. You don't even have to, and mostly won't even damage the silicon except by biasing it electrically. Scratching the top of the die is enough to brick it.

Btw, silicon is not rainbow colored. The color actually depends on the thickness of the silicon layer. For example, brown silicon has a thickness of approx. ~750Å
Edited by TheBlademaster01 - 12/5/12 at 4:39pm
post #9673 of 10523
I know its not actually rainbow colored, I work at a Micron fab, but thats how probably 99% of the people have actually 'seen' a silicon wafer. Finished, topside, as some Intel exec is holding it at a news conference. A pure silicon wafer is more of a dark silver color than anything. The only way what we see of a GPU/CPU die could actually be silicon would be if it was the bottom but I doubt that. If the height of a packaged Intel chip is the width of one of these posts, the part with transistors on it would be like this -- wide. mm vs um.
post #9674 of 10523
Quote:
Originally Posted by mmonnin View Post

I know its not actually rainbow colored, I work at a Micron fab, but thats how probably 99% of the people have actually 'seen' a silicon wafer. Finished, topside, as some Intel exec is holding it at a news conference. A pure silicon wafer is more of a dark silver color than anything. The only way what we see of a GPU/CPU die could actually be silicon would be if it was the bottom but I doubt that. If the height of a packaged Intel chip is the width of one of these posts, the part with transistors on it would be like this -- wide. mm vs um.

Assuming a flip chip package, you'd typically see the molded layer on top of the actual die. If the top layer would have been silicon (non-oxidated, photoresist) it would conduct. But like I said, you don't have to damage the active regions to brick a die.

I also did some fabbing last year as part of a college course, was more involved with logic design though. Interesting and mind boggeling process even though it had only had relatively few steps tongue.gif. It was even more complex than I first anticipated, the waferstepper in the fabbing lab could print our entire country at a resolution of 2cm in a matter of seconds. Just gave me an idea of how complex the doping process was lol tongue.gif.

What is your function/position if I may ask smile.gif?
post #9675 of 10523
At the end of fab processing, probably the only thing conductive are the bond pads, which are wire bonded later. Later the bottom of the wafer gets polished down to thin the wafer. And what we see wouldnt be the bottom anyway as there's probably a voltage applied the substrate of a CPU/GPU. I busted out the MM and tested an old athlon core and it didn't read any resistance unlike the pins or other contacts on the chip packaging.

I'm an Engineer in basically an inline QA group. We inspect the wafers, product and non-product, for defects. Particles and bad patterning of any sorts.

You are in the home country of ASML, the leader in semiconductor photolithography equipment. Those things print a 300mm wafer in like 20 seconds or something with an alignment overlay of 2-3um. One of my best friends lives over there in Eindhoven.
post #9676 of 10523
I should be subbed in the AMD cat now, if aNOOBis did it correctly.

Overall, we're not doing too bad.


Btw, found this picture in one of the team threads, presumably from the last update of Nov. Shows us having 7.955 million, with the 8057 gone (for now?) we're not gonna come close to this in December though:

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post #9677 of 10523
2nd place this early in the month is never a bad thing biggrin.gif I havent been killing it with points like last month but Ive had a steady 28k ppd average so far this month. Id be happier if I could get a few 55-70k ppd units a day instead of all 24-33k ppd units

Whats the all time record for most tc points in a month?
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post #9678 of 10523

I would be surprised if we didn break that record last month. I think 6.5mil has been the highest I've seen in July.

post #9679 of 10523
Quote:
Originally Posted by labnjab View Post

Whats the all time record for most tc points in a month?

Our score in November, by quite some margin.
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post #9680 of 10523
Even higher then when big advantage worked? Thats awesome
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