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About VRMs & Mosfets / Motherboard Safety with 125W+ TDP processors - Page 83

post #821 of 1100
I enjoyed your whole write up! A great threat to point to when certain situations arise!
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post #822 of 1100
Quote:
Originally Posted by xd_1771 View Post
Is it from Gigabyte?
That's actually a 6+2+2 (x86 processor + graphics procesor + IMC)
that is what i thought it was 6+2+2 originally as well, but something didn't add up, so i check to see how many chokes were linked to each bank, and there were 8 linked together, and then 2 linked together. So i looked at what GB advertised, and they said 8+2, it is a 8+2 phase for the APU, the GPU i guess gets a steady voltage or just the same as the CPU voltage or CPU-NB voltage.

Here is what i find weird. The "main" PWM has one phase with integrated drivers for the CPU-NB, then it has two phases with integrated drivers for the CPU cores. THEN the "main" PWM has another 2 phases for the CPU, but without drivers. There are NO drivers lol.

Then under the heatsink I found TWO MORE PWMs, little single phase with integrated drivers PWMs. Lined up just like MOSFETs. There are 20 MOSFETs total.

Anyways then i find that the two small PWMs ALSO are wired to the main PWM.

So now I am confused LOL.

Then there is one phase for the CPU PLL off to the lower right corner of the socket.

Anyways in BIOS there is 0 way to change the GPU's voltage. The only thing even close is APU PCI-E PLL called VDDP.
    
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post #823 of 1100

I forgot to check back to see if I got any answers.
Thanks for the suggestions kd, but what do you think about this motherboard:

(Asrock 870 Extreme3)
Same phases as the 870-iCafe and same heatsink but with an added USB 3.0 and SATA 6GBs (some future-proofing) for 10 USD more.
post #824 of 1100
pretty much the same board.
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post #825 of 1100
Thread Starter 
@ Sin0822: It seems like the CPU + GPU may share voltage and thus share resources with the main channelings... but wow, you're right, it does seem confusing

The way I see it: the 6 chokes on the left side of the socket are split phase to 3 channels to supply the CPU. 4 MOSFETs per channel, 3 channels, split inductors.
The 4 chokes on the upper side are split into 2 phases to supply the GPU portion and IMC portion. Thus they are not heatsinked. There are 2 channels, 4 MOSFETs per channel, and split inductors again. One channel supplies the GPU portion, other supplies IMC.

That's how I determine how it could be split phase between CPU & GPU. If it wasn't split phase... well to have the CPU portion heatsinked but IMC not makes sense, but to have some of the CPU portion heatsinked and some not, it doesn't make too much sense (3 of the channels would be heatsinked, one would be bare) To have 6 phases for CPU and a large 4 phases for the IMC, also definitely doesn't make sense; the IMC does not need that many channels.
Edited by xd_1771 - 6/23/11 at 11:18pm
post #826 of 1100
yea so, here is what i put together after a lot of probing and testing. The output voltage for outlined in red is the same, its the CPu core voltage, and the green is the CPU-NB voltage.



So it is 8+2, and i am guessing either the CPU and GPu use the same vcore (1.4v stock) to simplify things, or that the GPu runs off the CPU-NB voltage which is 1.125v stock. Then we have APU VDDP voltage the PCI-E PLL voltage for the APU.

I think, and I am quite certain how this works, the main PWM has its 2 phase integrated drivers and 2 phase NOT integrated (requires drivers), but is only using the Integrated drivers phases, so the main PWM is only operating in 2+1 phase mode. Then we have the other two PWMs, and their feedback circuitry + oscillation has to be synced, just like the ISL6617 allows for phase multiplication (its a "phase doubler" lol), OR they are just using the ISL6545s as drivers for the other two channels.

So in the end it has 4+1 channels, and since the drivers aren't integrated they can double each upper and lower gate FETs and operate as 4 phases, but double the output/half the load per phase. Which would make is a pretty nice design, except for the fact they could have just used two drivers, of course i have never seen Intersil drivers used, i have always seen their integrated drivers, or DrMOS. Either way they prob made use of ISL6545 b/c of the fact they probably had many already. Either way its teh most robust VRM I have seen for A75 chipset.

I will make a diagram for you tomorrow b/c this is just crazy weird, and i know you always like seeing new VRMs! lol just like me I am obsessed.
    
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post #827 of 1100
I'm just gonna say it right here.....

Told ya' so.
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post #828 of 1100
Thread Starter 


It's so crazy and weird it nearly doesn't make sense actually.... and yet if you really think about it, it may indeed be quite the genius

Though if you have seen pictures of what's under the heatsink on that A75 board, there are 12 MOSFETs, which should - judging from usual Gigabyte 4-transistor design - correspond to 3 channels.... not 4 (i.e. split into 6 inductors, but not 8)
I have a feeling the GPU may be using/sharing the CPU-NB voltage in this case. 40nm GPUs usually operate at the lower voltages closer to 1V so it does make sense, this is on 32nm GlobalFoundries process. Plus it may better explain why on many boards you will see the MOSFETs corresponding to 3 channels sinked (i.e. for the CPU portion), while 2 aren't (so it is more like a 3+2 phase than 4+1; if it was 4+1 then for the main PWM's you'd have 3 phases sinked but 1 not, that I find still doesn't make sense whatsoever since you create a weakness) [or in the case of this mobo, 6 channels are sinked and 4 aren't]. Then again, you did state something earlier about it indeed being 8+2 because of how they were linked; I am guessing you tested that yourself?

It's probably still marketed as 4+1 or 8+2 for simplification since that is what AMD users are familiar with.
Edited by xd_1771 - 6/24/11 at 2:45am
post #829 of 1100
hey, yea I have one of these A75 boards and a llano CPU. i will take a pic when i wake up. Its advertised as 8+2, but only 4+1 phases from the PWMs. Lets put it this way, it puts out as much current as a 8+2 phase design, but operates as a 4+1 phase VRM. That is how VRMs like this operates, opposed to the Intel designs, where the 24 phase designs are true 24 phase designs even though the PWM is only 6 phase, and that is because they use those ISL6617 ICs that actually allow the PWM channels to divide into two separate and sequential phases, so in the end you have a true 24 phase waveform with every pair of FETs pulsating after each other. Here we have 4 FETs pulsating at the same time. Here we also lack the ISl6617.


I think on this board sinking was done as a courtesy lol, aluminum costs money you know.

Anyways the main PWM is a 4+1 phase PWM, the +1 phase has integrated drivers, and 2 of the 4 have integrated drivers.

Tomorrow I am going to see what pins the PWMs link to and that way i can tell exactly how it operates. ill take a pic of everything for you too, b/c this is weird ass design.

There are a total of 20 Low RDSon MOSFETs. They are paired high side and low side, and they did not use a third FET to switch in place of a driver.
    
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post #830 of 1100
Thread Starter 
Split-inductor (4+1 phase, 8+2 current), I'm aware of what that is; it's common among regular AM3/etc boards.

Here is how I explain my new "3+2 phase" theory:


This is the A75-D3H. You can see that this screenshot seems to further support my "3+2 phase" theory (3 phase CPU portion @ 1.4V, 2 phase GPU & IMC portion at ~1.1V). You can see that the mounting holes for the heatsink go over the MOSFETs serving the 3 primary channels. Meanwhile, on the north side of the socket, there are two phases using a smaller 2 transistor + 1 driver (or 3 transistor) design, with no choice for heatsink mounting. With the transistor design being totally different for phase # 4 and of course not covered by heatsink, there is no way this is a 4+1 phase design. On the A75-UD4H, this design would be the same except that the inductors are split (3+2 phase, 6+4 current), the 3 CPU channels are indeed heatsinked, and the 2 north-side channels make use of 4 transistors/drivers instead of 3 for better power output.

Tomorrow's test of where the +/- currents flow through each other should prove which channels belong to which.
Edited by xd_1771 - 6/24/11 at 2:51am
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