yea so, here is what i put together after a lot of probing and testing. The output voltage for outlined in red is the same, its the CPu core voltage, and the green is the CPU-NB voltage.
So it is 8+2, and i am guessing either the CPU and GPu use the same vcore (1.4v stock) to simplify things, or that the GPu runs off the CPU-NB voltage which is 1.125v stock. Then we have APU VDDP voltage the PCI-E PLL voltage for the APU.
I think, and I am quite certain how this works, the main PWM has its 2 phase integrated drivers and 2 phase NOT integrated (requires drivers), but is only using the Integrated drivers phases, so the main PWM is only operating in 2+1 phase mode. Then we have the other two PWMs, and their feedback circuitry + oscillation has to be synced, just like the ISL6617 allows for phase multiplication (its a "phase doubler" lol), OR they are just using the ISL6545s as drivers for the other two channels.
So in the end it has 4+1 channels, and since the drivers aren't integrated they can double each upper and lower gate FETs and operate as 4 phases, but double the output/half the load per phase. Which would make is a pretty nice design, except for the fact they could have just used two drivers, of course i have never seen Intersil drivers used, i have always seen their integrated drivers, or DrMOS. Either way they prob made use of ISL6545 b/c of the fact they probably had many already. Either way its teh most robust VRM I have seen for A75 chipset.
I will make a diagram for you tomorrow b/c this is just crazy weird, and i know you always like seeing new VRMs! lol just like me I am obsessed.