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[Endgadget] Intel to spend $5 billion on new 14nm fab in Arizona - Page 6

post #51 of 131
Quote:
Originally Posted by Mr.Pie View Post
What was the point of posting that? We all now that transistor sizes have decreased. I'm asking whether or not you believe Moore ever claimed how much they would decrease in a unit of time since it was being implied by an earlier poster.
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post #52 of 131
Thread Starter 
Quote:
Originally Posted by sccr64472 View Post
What was the point of posting that? We all know that transistor sizes have decreased. I'm asking whether or not you believe Moore ever claimed how much they would decrease in a unit of time since it was being implied by an earlier poster.
oh right
i misunderstood what you said then
eyes playing funny tricks on me

and to your question; i don't know actually
as long as it means better performance for us
post #53 of 131
Ehh. Intel's impressed me so much over the years that this really isn't exciting anymore. I can no longer expect anything less than "totally amazing" from them. Even when they totally screw something up I have the same reaction.
I guess I've finally crossed over from a fan-boy to an acolyte.
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post #54 of 131
Quote:
Originally Posted by 5entinel View Post
Is this really necessary?
I mean,hardware is moving way.........too fast for software to catch up.
lol
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post #55 of 131
I'm having a hard time trying to imagine what exactly gets smaller.
post #56 of 131
Quote:
I'm not disputing the fact that transistor sizes have decreased over time since companies need to keep power consumption and chip size to a minimum.
Power consumption is only a fairly recent main reason to shrink transistor sizes. For a long time the main goal of shrinking transistors was to pack more devices on a die therefore enabling you to do so much more with the device.

Quote:
What I'm asking is whether or not you're trying to state that Moore claimed a certain size reduction in a given period of time.
It essentially does. Moore's law refers to the density of transistors per unit area doubling. For example, draw a rectangle with 1cm^2 area. The easiest way to do this is to draw each side as 1cm. This square has one partition. Now, you want to "double the density of partitions" to 2 partitions in a 1cm^2 area. Since you only have 1cm^2 area to double the partitions within it you'd just divide by 2 to get .5cm^2 for each partition. For a .5cm^2 square each of the sides would come out to .707cm, hence the "~.7" scaling factor I mentioned earlier. In order to follow Moore's law, you have to scale by ~.7. If you look at the history of transistor scaling you can see it follows this rule quite well:

90nm x .7 = 63 (65nm)
65nm x .7 = 45.5 (45nm)
45nm x .7 = 31.5 (32nm)
32nm x .7 = 22.4 (22nm)

One aspect of Moore's Law that should be noted is that it's essentially a self fulfilling prophecy. In the earlier days their technology limited them to the doubling of transistor densities every 1-2 years. Currently I'm sure they could do it quicker, but with the dire importance of roadmaps to keep the industry well coordinated this is the pace that everybody has agreed on.

Quote:
I'm having a hard time trying to imagine what exactly gets smaller.
"45nm, 32nm, ect" refer to "minimum feature lengths," which is the smallest the lithography process can make something on a wafer. With CMOS devices this refers to the channel length of the MOSFET. The shorter the channel length you make, the less space a transistor takes up therefore more of them can be placed in the same area.
Edited by farkle0079 - 2/20/11 at 1:21am
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post #57 of 131
Quote:
Originally Posted by videoman5 View Post
14nm? Already? Wat.

Edit: Starting in 2013, which means that 14nm won't be here until, at the soonest, 2014.
My Q9450 may actually make it to 2014 as far as games are concerned.
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post #58 of 131
You guys do realize 10nm is the bottom line as of yet.
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post #59 of 131
This was on PBS Nightly Business Report Friday night so it's old to me

New fab = more jobs
    
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post #60 of 131
wait only 4000 jobs
dang what about the rest of arizona?
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