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[NM] New Bulldozer Leaks!!!  

post #1 of 24
Thread Starter 
I'm not saying anything posted is letgit/real/confirmed, but I'm offering them as leaked info, nothing more, nothing less!

(Had to translate the page to get the stuff!)
Quote:
AMDZone.com claimed that AMD server and workstation where the global business manager John Fruehe learned exclusively on its next-generation processor architecture, "bulldozer" (Bulldozer) exclusive information, including a more detailed framework for technical and practical performance.

至于为什么现在公开,John Fruehe表示虽然推土机架构处理器还有一段时间才会发布,但他们对新品信心十足,相信Intel的下一代芯片(Sandy Bridge)也不是对手。 As to why now open, John Fruehe said that although the structure of the processor some time bulldozers will not be published, but their new confidence, I believe the next generation of Intel chips (Sandy Bridge) are not rivals.

New details of the AMD processor architecture bulldozers, performance, exclusive exposure

一、推土机架构总览 First, the bulldozer structure overview

去年11月底的年度分析师会议上, AMD首次公布了推土机架构的一些技术细节 , 之后我们又做了补充分析 。 The end of November last year, the annual analyst meeting, AMD announced a bulldozer for the first time some of the technical details of the framework , then we made a supplementary analysis . 今天,AMD提供了更详细的架构图。 Today, AMD provides a more detailed chart.

New details of the AMD processor architecture bulldozers, performance, exclusive exposure

每一个推土机模块都包括两个整数核心与一个浮点单元,其中每个整数核心有四条完整的整数管线,每条管线内又有一个算术逻辑单元(ALU)和一个地址生成单元(AGU),可以执行x86整数代码、存储指令以及合并执行SSE、AVX整数代码,这也是最大的变化。 Each module contains two integers Bulldozer core and a floating point unit, where each integer integer core has four full lines, each line have an arithmetic logic unit within the (ALU) and an address generation unit (AGU), integer code can execute x86, storage instructions and the merger of the implementation of SSE, AVX integer code, which is the biggest change.

浮点单元内有两个128位宽范围的FMAC单元,可以执行新的积和熔加运(FMA)指令或者浮点加法与乘法操作,这样既能降低功耗,也能提高简单操作的吞吐量。 Floating-point unit has two 128-bit wide range of FMAC unit can execute a new product and melt plus transportation (FMA) instructions or floating-point addition and multiplication operation, this would both reduce power consumption, simple operation can improve the throughput volume. 据AMD解释,两个FMAC单元既可以被两个核心整数的两个线程并行使用,也能被一个线程循环使用。 According to AMD explained that the two FMAC units can either be two core integers using two threads in parallel, one thread can also be recycled.

每个整数核心内还都有自己的16KB一级缓存和载入存储单元(LSU),其中后者负责管理来自自身所在整数核心以及浮点单元的所有存储请求,每个核心能执行两个在载入和一个存储操作,都是最高128-bit。 Each integer core also has its own 16KB internal cache and loading the storage unit (LSU), the latter of which is responsible for managing the core from its integer and floating point unit where all storage requests, each core can execute two In the load and a store operation, are the highest 128-bit. 相比于K10架构,推土机的LSU还能执行数据和地址的推测。 Compared to the K10 architecture, bulldozers, LSU also performs data and address the speculation.

为了减少分支预测的错误和由此造成的拾取操作延迟,分支预测单元也有所改进,能够在每个时钟周期内预测多个分支并发送代码预取。 Branch prediction in order to reduce errors and delays resulting pickup operation, branch prediction unit has been improved to predict multiple branches in each clock cycle and sends the code prefetch.

对性能提升贡献很大的另一个重要特性是各个单元能运行在不同频率上,可以关闭任何闲置的子单元并调整缓存容量(比如将一级缓存从四路16KB关闭成双路8KB),还有一个电源控制器负责跟踪每个子单元的载入和功耗情况,这叫作应用电源管理(APM)。 Great contribution to the performance of another important feature is the various units can run on different frequencies can be turned off any idle and adjust the cache sub-units (such as the one from the four-way 16KB cache off into a two-way 8KB), also a power controller for each sub-unit responsible for tracking the load and power conditions, which is called the application of power management (APM).

最后是五级缓存架构: Finally, five cache architecture:

- 零级缓存:每个线程(或核心)4KB 8路关联; - Zero-level cache: each thread (or core) 4KB 8-way associative;

- 一级缓存:每个核心16KB 4路关联数据缓存,延迟1个循环;每个模块128KB 4路关联; - Cache: each core 16KB 4-way associative data cache, 1 cycle latency; each module 128KB 4-way associative;

- 二级缓存:每个模块2MB 8路关联,两个核心共享,全速; - Secondary Cache: 2MB 8-way associative each module, two cores sharing, full-speed;

- 三级缓存:所有核心共享8MB,延迟24个循环,每个时钟循环可同时处理最多两个请求; - Level III cache: all the core shared 8MB, delay of 24 cycles, each clock cycle can handle up to two requests;

- 四级缓存:桌面黑盒版以及服务器Opteron都将通过芯片堆栈新增四级缓存,容量32MB或者64MB。 - Level Cache: black-box version of the desktop and server Opteron chip stack will be through the new four buffer capacity of 32MB or 64MB.

二、新接口新工艺 Second, the new interface, new technology

推土机核心在基于32nm SOI工艺得初期试产中表现得异常可靠,因此AMD正在试验使用28nm Bulk工艺进行小批量生产,但既未确认也未否认最终是否会使用28nm。 Bulldozer core 32nm SOI process was based on the initial test is extremely reliable performance in production, AMD is experimenting with using the 28nm Bulk Process for small batch production, but neither confirmed nor denied whether it will eventually use 28nm.

New details of the AMD processor architecture bulldozers, performance, exclusive exposure

不过AMD确认,推土机处理器将采用Socket AM3+接口,941个针脚,不同于目前938个针脚的Socket AM3接口,其好处是可以支持DDR3-1866内存和高级节能技术,而且AM3+将是。 However, AMD confirmed that bulldozers will use Socket AM3 + processor interface, 941 pins, unlike the current 938-pin Socket AM3 interface, its benefits can support DDR3-1866 memory, and advanced energy-saving technology, and AM3 + will be.

AM3+ 将是AMD的最后一代针脚栅格阵列(PGA)封装,之后将改用触点栅格阵列(LGA),等到Fusion融合处理器降临的时候就会使用LGA AF1新接口,触点多达1591个,支持DisplayPort 1.2标准、PCI-E 3.0规范(32条信道)、四通道内存。 AM3 + will be AMD's last generation of pin grid array (PGA) package, and then will switch to contact grid array (LGA), until the time comes Fusion Fusion processors will use LGA AF1 new interface, up to 1591 contacts a support DisplayPort 1.2 standard, PCI-E 3.0 specification (32 channels), four-channel memory.

三、智能加速 Third, intelligent speed

Intel Core ix家族支持Turbo Boost,AMD Phenom II X6也祭出了Turbo Core,都是多核心智能加速技术,可以自动关闭部分核心,并提高剩余核心的频率。 Intel Core ix family support Turbo Boost, AMD Phenom II X6 also dishing out a Turbo Core, are intelligent multi-core acceleration technology, can automatically shut down part of the core, and increase the frequency of the remaining core.

推土机则提供了两个级别的智能加速,其一是在每个模块内,可以动态调整每条整数管线的能耗,能将其中一个整数核心彻底关闭,并加速另一个整数核。 Bulldozers provides two levels of intelligence to accelerate, one in each module, you can dynamically adjust the energy consumption of each integer pipeline, which can completely shut down an integer core and accelerate the other integer core.

AMD保证这会带来0.6-1.6GHz不等的模块核心频率提升,幅度30-35%,比如: AMD to ensure that this will bring 0.6-1.6GHz frequency range to enhance the core modules, ranging from 30-35%, such as:

2.0GHz->2.6GHz +30% 2.0GHz-> 2.6GHz +30%
2.4GHz->2.6GHz +33% 2.4GHz-> 2.6GHz +33%
2.8GHz->3.8GHz +35% 2.8GHz-> 3.8GHz +35%
3.2GHz->4.2GHz +31% 3.2GHz-> 4.2GHz +31%
3.6GHz->4.6GHz +33% 3.6GHz-> 4.6GHz +33%
4.0GHz->5.6GHz +30% 4.0GHz-> 5.6GHz +30%

第二个级别则是针对整体主频,会在高负载的时候有规律地逐步提高200MHz,直到上限。 The second level is for the overall frequency, when in the high-load gradually increase regularly 200MHz, until the ceiling. 如果一个模块在最低能耗状态,其他模块就能超频两三个级别。 If a module in the lowest power state, other modules can be two or three levels of overclocking.

一旦超过功耗或者散热限制,主频就会自动递减200MHz,直到低于限制。 Once more than power or cooling constraints, automatically decreasing frequency 200MHz, until the lower limit. 比如: For example:

2.0GHz->3.2GHz +60% 2.0GHz-> 3.2GHz +60%
2.4GHz->3.8GHz +58% 2.4GHz-> 3.8GHz +58%
2.8GHz->4.4GHz +57% 2.8GHz-> 4.4GHz +57%
3.2GHz->4.8GHz +50% 3.2GHz-> 4.8GHz +50%
3.6GHz->5.4GHz +50% 3.6GHz-> 5.4GHz +50%
4.0GHz->5.8GHz +45% 4.0GHz-> 5.8GHz +45%

四、性能实测 Fourth, the performance measured

终于到了性能测试部分,考察对象包括基于推土机架构的桌面版Zambezi 2.8GHz、Zambezi 3.2GHz、Zambezi BE 3.2GHz(有四级缓存的黑盒版)以及服务器版Interlagos 3.2GHz。 Finally to the performance testing part of the study objects include architecture-based desktop bulldozers Zambezi 2.8GHz, Zambezi 3.2GHz, Zambezi BE 3.2GHz (there are four black-box version of the cache) and the Server Edition Interlagos 3.2GHz. 柱状图可以说明一切,就不废话了。 Histogram can explain everything, is not nonsense.

S01023254.png

S01023260.png

S01023268.png

S01023274.png

S01023281.png

S01032281.png

S01032287.png

S01032293.png

S01032299.png

S01032306.png

S01033853.png

S01033867.png

S01033873.png
Quote:
It can be seen from the test, the power of bulldozers really fierce, almost every rule in the performance of test items, power consumption is quite low. 不要忘了,这只是预览性质的早期样品的表现,最终成品肯定还会更优秀。 Do not forget, this is only an early preview of the nature of the performance of the sample, the final product will definitely better. 唯一可惜的就是没有加入和六核心Core i7-980X的对比。 The only pity is not a member and six-core Core i7-980X contrast.

Source
Edited by _GTech - 2/19/11 at 9:05pm
The Rock
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post #2 of 24
Nngggghhhh!
post #3 of 24
Thread Starter 
Quote:
Originally Posted by Cata1yst;12452500 
Nngggghhhh!

What, it's fake?
The Rock
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post #4 of 24
I call lies.
Could at least compare to 2600k..

Also 'exclusively exclusive information' amused me.
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post #5 of 24
Source link, please?
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post #6 of 24
So... must contain excitement... Will coolers designed for AM3 work with AM3+?
post #7 of 24
Thread Starter 
Coming Chunky Chimp

============================

OMG, this is an april fools joke, grrrrrrrrrrrrrrrrr!


facepalm.jpg
Edited by _GTech - 2/19/11 at 9:08pm
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Quote:
Originally Posted by TFL Replica;12452537 
So... must contain excitement... Will coolers designed for AM3 work with AM3+?

Same cooler scheme since 754/939..
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post #9 of 24
Interlagos definitely looks badass, but I can't feel not being quite so impressed with Zambezi. It's definitely better than current Intel architecture, but not by as much as I was hoping. I can't wait for more reviews to pit 'em against SB, IB, LGA2011(whatever it's called).
post #10 of 24
Wonder if the server chips will work on Enthusiast boards, like back in the 939 days. thinking.gif

Interlagos!
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