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[NM] New Bulldozer Leaks!!! - Page 2  

post #11 of 24
Interesting April fools joke.
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post #12 of 24
dame the interlagos

but DAME 4ghz boost the 5.6?
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post #13 of 24
isnt i7-920 stock at 2.66ghz?...

they should compare them all at 3.2 ghz.

wish they did this for sandy bridge b4 too.
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post #14 of 24
If any of this turns out to be remotely true, I'll be buying options like there's no tomorrow. This would drive the stock up so freaking fast.
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post #15 of 24
DDR3-1866 stock support? I wonder how well the IMC can handle memory overclocks then?

Also, nice power consumption figures, if true.

Quote:
Originally Posted by TH3 original View Post
isnt i7-920 stock at 2.66ghz?...

they should compare them all at 3.2 ghz.

wish they did this for sandy bridge b4 too.
Yeah, but the i7 975 is 3.33ghz, if you want something closer to 3.2ghz to compare with.
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post #16 of 24
You know google chrome translates.



New details of the AMD processor architecture bulldozers, performance, exclusive exposure

Driving home [original] Author: Wen top Q Editor: Q 2010-04-02 13:04:56 Loading the top of the text [delivery]
AMDZone.com claimed that AMD server and workstation where the global business manager John Fruehe learned exclusively on its next-generation processor architecture, "bulldozer" (Bulldozer) exclusive information, including a more detailed framework for technical and practical performance.

As to why now open, John Fruehe said that although the structure of the processor some time bulldozers will not be published, but their new confidence, I believe the next generation of Intel chips (Sandy Bridge) are not rivals.



First, the bulldozer structure overview

The end of November last year, the annual analyst meeting, AMD announced a bulldozer for the first time some of the technical details of the framework , then we made a supplementary analysis . Today, AMD provides a more detailed chart.



Each module contains two integers Bulldozer core and a floating point unit, where each integer integer core has four full lines, each line have an arithmetic logic unit within the (ALU) and an address generation unit (AGU), integer code can execute x86, storage instructions and the merger of the implementation of SSE, AVX integer code, which is the biggest change.

Floating-point unit has two 128-bit wide range of FMAC unit can execute a new product and melt plus transportation (FMA) instructions or floating-point addition and multiplication operation, this would both reduce power consumption, simple operation can improve the throughput volume. According to AMD explained that the two FMAC units can either be two core integers using two threads in parallel, one thread can also be recycled.

Each integer core also has its own 16KB internal cache and loading the storage unit (LSU), the latter of which is responsible for managing the core from its integer and floating point unit where all storage requests, each core can execute two In the load and a store operation, are the highest 128-bit. Compared to the K10 architecture, bulldozers, LSU also performs data and address the speculation.

Branch prediction in order to reduce errors and delays resulting pickup operation, branch prediction unit has been improved to predict multiple branches in each clock cycle and sends the code prefetch.

Great contribution to the performance of another important feature is the various units can run on different frequencies can be turned off any idle and adjust the cache sub-units (such as the one from the four-way 16KB cache off into a two-way 8KB), also a power controller for each sub-unit responsible for tracking the load and power conditions, which is called the application of power management (APM).

Finally, five cache architecture:

- Zero-level cache: each thread (or core) 4KB 8-way associative;

- Cache: each core 16KB 4-way associative data cache, 1 cycle latency; each module 128KB 4-way associative;

- Secondary Cache: 2MB 8-way associative each module, two cores sharing, full-speed;

- Level III cache: all the core shared 8MB, delay of 24 cycles, each clock cycle can handle up to two requests;

- Level Cache: black-box version of the desktop and server Opteron chip stack will be through the new four buffer capacity of 32MB or 64MB.

Second, the new interface, new technology

Bulldozer core 32nm SOI process was based on the initial test is extremely reliable performance in production, AMD is experimenting with using the 28nm Bulk Process for small batch production, but neither confirmed nor denied whether it will eventually use 28nm.



However, AMD confirmed that bulldozers will use Socket AM3 + processor interface, 941 pins, unlike the current 938-pin Socket AM3 interface, its benefits can support DDR3-1866 memory, and advanced energy-saving technology, and AM3 + will be.

AM3 + will be AMD's last generation of pin grid array (PGA) package, and then will switch to contact grid array (LGA), until the time comes Fusion Fusion processors will use LGA AF1 new interface, up to 1591 contacts a support DisplayPort 1.2 standard, PCI-E 3.0 specification (32 channels), four-channel memory.

Third, intelligent speed

Intel Core ix family support Turbo Boost, AMD Phenom II X6 also dishing out a Turbo Core, are intelligent multi-core acceleration technology, can automatically shut down part of the core, and increase the frequency of the remaining core.

Bulldozers provides two levels of intelligence to accelerate, one in each module, you can dynamically adjust the energy consumption of each integer pipeline, which can completely shut down an integer core and accelerate the other integer core.

AMD to ensure that this will bring 0.6-1.6GHz frequency range to enhance the core modules, ranging from 30-35%, such as:

2.0GHz-> 2.6GHz +30%
2.4GHz-> 2.6GHz +33%
2.8GHz-> 3.8GHz +35%
3.2GHz-> 4.2GHz +31%
3.6GHz-> 4.6GHz +33%
4.0GHz-> 5.6GHz +30%

The second level is for the overall frequency, when in the high-load gradually increase regularly 200MHz, until the ceiling. If a module in the lowest power state, other modules can be two or three levels of overclocking.

Once more than power or cooling constraints, automatically decreasing frequency 200MHz, until the lower limit. For example:

2.0GHz-> 3.2GHz +60%
2.4GHz-> 3.8GHz +58%
2.8GHz-> 4.4GHz +57%
3.2GHz-> 4.8GHz +50%
3.6GHz-> 5.4GHz +50%
4.0GHz-> 5.8GHz +45%

Fourth, the performance measured

Finally to the performance testing part of the study objects include architecture-based desktop bulldozers Zambezi 2.8GHz, Zambezi 3.2GHz, Zambezi BE 3.2GHz (there are four black-box version of the cache) and the Server Edition Interlagos 3.2GHz. Histogram can explain everything, is not nonsense.

VI Summary

It can be seen from the test, the power of bulldozers really fierce, almost every rule in the performance of test items, power consumption is quite low. Do not forget, this is only an early preview of the nature of the performance of the sample, the final product will definitely better. The only pity is not a member and six-core Core i7-980X contrast.
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post #17 of 24
Quote:
Originally Posted by _GTech View Post
Coming Chunky Chimp

============================

OMG, this is an april fools joke, grrrrrrrrrrrrrrrrr!
Uh, what?
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post #18 of 24
If this is true my upgrades look rather but I dunno about it...and would def be nice if they brought back the old style from 939 where opti's would run on standard boards
    
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post #19 of 24
abit early for april fools dont u think?
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post #20 of 24
Quote:
Originally Posted by Chunky_Chimp View Post
Uh, what?
Classic!
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