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[AMD] What to Expect From AMD at ISSCC 2011 - Page 2

post #11 of 32
Quote:
Originally Posted by Martkilu View Post
Stuff I've gleaned:
JF-AMD pretty much confirmed these higher clocks speeds for BD parts in another thread as well. He didn't come right out and say it, but he may as well have. I am expecting 4Ghz stock with Turbo Core 2.0 enabled. The big question left is OC potential and instructions per clock improvements, at least for me.

Quote:
Originally Posted by JF-AMD View Post
http://www.cpu-world.com/news_2011/2...rocessors.html

Looks like they will have a top end of 10 cores at 2.4GHz.

We have 12 cores at 2.5GHz. And 8 cores at 2.6GHz.

And bulldozer will bring 16 cores and 12-cores, I won't say anything about clocks, but if I have 12-cores higher than them with 45nm, just wait for 32nm.
post #12 of 32
Don't disappoint me AMD!
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post #13 of 32
if any news is expected from AMD at any show/conference/whatever is Info on BULLDOZER !!!
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post #14 of 32
Interesting.
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post #15 of 32
Can anyone extrapolate what this means as opposed to phenom II in terms of Performance?

Quote:
A 40-instruction out-of-order scheduler issues four operations per cycle and supports single-cycle operation
wakeup. The integer execution unit supports single-cycle bypass between four functional
units. Critical paths are implemented without exotic circuit techniques or heavy reliance on full-custom
design. Architectural choices minimize power consumption.
    
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post #16 of 32
Quote:
Originally Posted by OcCam View Post
Can anyone extrapolate what this means as opposed to phenom II in terms of Performance?
Not sure on most of it, but it sounds like BD will have a max of 4 instructions per clock as opposed to Deneb/Thuban's ~3, I think, instructions per clock. I could be reading it wrong though. The instructions per clock on Phenom II's in real world scenarios are more like ~2.2-2.5 from what I have read, so if BD can actually achieve 4 it should be quite a bit faster per clock cycle. If I am not mistaken i7's are max 4 instructions per clock as well, again that is max and probably don't reach that in real world tests. The other stuff is way over my head, no idea what it all means.

I am guessing mostly though, I don't know much about it.
post #17 of 32
Quote:
Originally Posted by OcCam View Post
Can anyone extrapolate what this means as opposed to phenom II in terms of Performance?
Hard to say. CPUs on this scale are so complex that an overview of a few design choices can't really give any meaningful insight into the overall performance of the CPU.

Source: I've designed a working pipelined MIPS CPU in VHDL.
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post #18 of 32
Thread Starter 
Quote:
Originally Posted by OcCam View Post
Can anyone extrapolate what this means as opposed to phenom II in terms of Performance?
Well atleast we know it's better than Phenom II.
>dat smooth feel
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>dat smooth feel
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post #19 of 32
Can someone tell me what time this event is on and timezone would be good thanks.
    
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post #20 of 32
Thread Starter 
Quote:
Originally Posted by theodorou View Post
Can someone tell me what time this event is on and timezone would be good thanks.
Pretty sure all the info you need is here: http://isscc.org/
>dat smooth feel
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>dat smooth feel
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