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How does the inside of modern processors work?

post #1 of 12
Thread Starter 
I posted this in the wrong forum earlier, but...

Does anyone know of a good diagram or link that can explain how an 1156/1366 or all CPUs work, and how (if at all) they differ from older cpus?

I understand that there are three basic components involved; the I/O unit, control unit and ALU. The I/O unit manges the instructions and data that come into the processor. The control unit is in charge of the activities inside the actual processor, and the ALU is what does all the calculations.

I'm not 100% sure what the registers do, though. I know that they work like SDRAM, but how do they differ from the static RAM that is the CPU's cache? I know the cache is internal memory that holds data and instructions that the CPU needs next so that it can be accessed quicker, but that is pretty much the extent of my knowledge.

P.S. Where is the FPU in all of this?
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post #2 of 12
they basically work the same bro with a few modern innovations
    
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post #3 of 12
This is about as detailed as you're going to get:
Nehalem_Die_callout.jpg

Otherwise you would have to work at intel. They're not just going to release a schematic of something they've spent billions of dollars on.
    
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post #4 of 12
Thread Starter 
Quote:
Originally Posted by Klue22;12469950 
This is about as detailed as you're going to get:
Nehalem_Die_callout.jpg

Otherwise you would have to work at intel. They're not just going to release a schematic of something they've spent billions of dollars on.

Haha. yeah I know that they wouldn't just reveal how they came up with their technology. I just wanted to know exactly how data and instructions flow through a processor.
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post #5 of 12
Quote:
Originally Posted by FreeWillzyx;12470786 
Haha. yeah I know that they wouldn't just reveal how they came up with their technology. I just wanted to know exactly how data and instructions flow through a processor.

This. I've been curious as well.

And where's L1 and L2 in the diagram?
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post #6 of 12
Quote:
Originally Posted by Krusher33;12470825 
This. I've been curious as well.

And where's L1 and L2 in the diagram?

Each individual core has its own L1 and L2 ... you can see then in the lower right part of the two cores on the left and lower left part on the two cores on the right (not 100% sure thats them)
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post #7 of 12
http://computer.howstuffworks.com/microprocessor.htm

Love this website, has a wealth of information on pretty much anything. smile.gif
Edited by jonjryjo - 2/21/11 at 11:49am
post #8 of 12
Thread Starter 
Quote:
Originally Posted by Cryptedvick;12470879 
Each individual core has its own L1 and L2 ... you can see then in the lower right part of the two cores on the left and lower left part on the two cores on the right (not 100% sure thats them)

Maybe. I know L1 is on the actual processor die, and L2 is in the processor package, but off the die making it further away from and slower then L1. And L3 cache is also in the package just further from the processor core and slower than L2 and shared among all the cores, where each core has it's own L1 and L2.
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post #9 of 12
Thread Starter 
I'm just going to take a guess...

I assume that, data and instructions enter and leave the CPU through the I/O unit (hence input/output) via front side bus. The control unit controls everything inside the processor, so I'm not too sure about what it exactly does. Does it just dictate where the data/instructions go? For example, which core it goes to and which ALU in said core, or whether or not it gets stored in the cache? I'm assuming it just controls everything in the CPU.

Than it goes to the ALU via internal bus where all the calculations are done. The registers (like RAM) hold data, instructions and addresses that the ALU is currently processing.

As for the cache, it's obviously memory in the CPU which holds data that the CPU predicts it will need next...

So how far off am I? Does anybody have any corrections or things to add? Not knowing is really bothering me. Thanks.
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post #10 of 12
Quote:
Originally Posted by FreeWillzyx;12474078 
Maybe. I know L1 is on the actual processor die, and L2 is in the processor package, but off the die making it further away from and slower then L1. And L3 cache is also in the package just further from the processor core and slower than L2 and shared among all the cores, where each core has it's own L1 and L2.

L2 cache is on die on modern CPUs.. Hasn't been that way since Pentium 1-2 days AFAIK. Pretty sure L3 is considered "on die" as well.
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