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AVX Instruction performance increase?

post #1 of 11
Thread Starter 
Is there one? confused.gif
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post #2 of 11
There will be if they start using it, until then no.
 
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post #3 of 11
Quote:
Originally Posted by dave12;12500223 
Is there one? confused.gif

I thought AVX Instruction would debut with SB and Bulldozer chips. Please correct me if I am wrong.
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post #4 of 11
The new bigadv core coming out soon... perhaps it will be used then.
Quote:
Originally Posted by youra6;12500268 
I thought AVX Instruction would debut with SB and Bulldozer chips. Please correct me if I am wrong.
Yeah, SB is already out... who knows when BD will be...
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post #5 of 11
Thread Starter 
Quote:
Originally Posted by youra6;12500268 
I thought AVX Instruction would debut with SB and Bulldozer chips. Please correct me if I am wrong.

I have a i5 2500 in addition to the one in my sig. Was just curious if all the extra flops I get in IBT from AVX translated to f@h, and I don't have any sporty folding monitoring stuff so I have no idea what my tpf was prior to this morning.
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post #6 of 11
No theres nothing different for folding atm but hopefully that will change soon.
 
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post #7 of 11
BD 4 module CPUs will probably totally pwn LGA1155 Sandy Bridge quads/8threads in -bigadv folding with or without AVX due to having TRUE integer cores. AVX if ever used will probably see big gains in both cases.
post #8 of 11
I saw somewhere that someone had a bench posted with/without AVX, difference was about 60 Gflops vs 110 Gflops
    
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post #9 of 11
Thread Starter 
Quote:
Originally Posted by xd_1771;12500520 
BD 4 module CPUs will probably totally pwn LGA1155 Sandy Bridge quads/8threads in -bigadv folding with or without AVX due to having TRUE integer cores. AVX if ever used will probably see big gains in both cases.

For modules = four cores? I was waiting till tomorrow when I can watch AMD guy axplain it.
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post #10 of 11
Four modules = 8 integer cores. FPU & L2 cache shared at module-level, but integer cores (the ones that actually process pretty much everything) are separate. This is how the entire new architecture works. It is supposed to be a sort of hard-ware level SMT processing unlike HyperThreading, while having the same kind of die size increase as HyperThreading but being much better in performance.
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