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post #7111 of 10701
I don't know what was up previously, but I have the C states disabled and am getting around 10 points more in AS SSD than with them enabled, lol.
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post #7112 of 10701
Managed to make it ~40 minutes without blue screening (124 again) with the settings in my previous post.

Is it true that once you find your bootable PLL setting you should be able to leave it alone and only have to tweak VCCIO/VCORE afterwords? I was able to lower PLL to 1.55v and boot w/ no problems. I also increased VCCIO to 1.2 up from 1.15. How high is it safe to raise VCCIO? Am I already going too far? Could it be that my VCCIO is too high instead of too low?

Any suggestions?
post #7113 of 10701
Quote:
Originally Posted by Shiveron View Post

Managed to make it ~40 minutes without blue screening (124 again) with the settings in my previous post.
Is it true that once you find your bootable PLL setting you should be able to leave it alone and only have to tweak VCCIO/VCORE afterwords? I was able to lower PLL to 1.55v and boot w/ no problems. I also increased VCCIO to 1.2 up from 1.15. How high is it safe to raise VCCIO? Am I already going too far? Could it be that my VCCIO is too high instead of too low?
Any suggestions?

I have heard (just hearsay) that the highest you want raise this value is 1.2. But this seems to be the general concensus. As a point of reference, my VCCIO is at 1.09 at a stable 5100MHZ.
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post #7114 of 10701
Think I'm gonna have to back off for now anyways. Starting to hit the 85c range. This h70 is havin none of it. Though I'm half way through a 1792k run and only hitting 79 so it looks like I should still be able to keep a good oc up with ht on and spread spectrum disabled.
post #7115 of 10701
Quote:
Originally Posted by csm725 View Post

I don't know what was up previously, but I have the C states disabled and am getting around 10 points more in AS SSD than with them enabled, lol.

There is no reason in my understanding why C states would improve performance, unless its doing offline maintenance during C3/C6. From my understanding of the implementation, The C states are causing the port to slow down sort of like ASPM does(part of the protocol for SATA is autonegotiation of link speed) for the pci-e links(im noticing a lot of people are leaving ASPM turned on in there desktop. Telltale is motherboard tab on cpuz shows 8x or less link speed on the graphics card) which the fluctuations between idle/load on the bus will likely add noticeable graphics latency. It makes perfect sense to use ASPM on a laptop as keeping those pci-e lanes fired up all the time costs about 15 watts

Another setting that confuses me is a lot of people seem to be disabling NX/VT even tho windows 7 implements VT in software for its os functions if it doesnt have hardware (the security prompt is windows 7 when you start up certain programs is the program exiting the VM) It also implements a software version of NX using canaries if you dont have NX bit, so your in both cases from my understanding of implementation hurting performance.

here is a quote on what C6 does: Warning: Spoiler! (Click to show)
When the CPU enters this state it saves its entire architectural state inside a special static RAM, which is fed from an independent power source. This allows the CPU internal voltage to be lowered to any value, including 0 V, what would completely turn off the CPU when it is idle. Then when the CPU is waked up it loads the previous state of all internal units from its special static RAM. Of course waking up the CPU from this state takes a lot longer than the previous states we discussed, but it is faster than turning off the computer and then turning it back on and loading the operating system, etc.

Notice that there is only one voltage line for the entire CPU (the only component with a different voltage source is the abovementioned special memory) and lowering or turning off the CPU voltage is an all-or-nothing kind of deal: if you turn off the CPU, you have to turn off it entirely when it goes into C6 mode.

The forthcoming Core i7 CPU (codename Nehalem) will have an embedded power control unit that allows the voltage for individual parts of the CPU to be reduced or turned off. For example, if only one processing core of the CPU is idle, it will be able to turn off just one of the cores, putting it on C6 mode.
C3: Warning: Spoiler! (Click to show)
The next state, Sleep (C3), cuts all internal clock signals from the CPU, including the clocks from the bus interface unit and from the APIC. This means that when the CPU is in the Sleep mode it can’t answer to important requests coming from the CPU external bus nor interruptions.

Intel CPUs and Turion 64 from AMD allow a C3 sub-mode called Deep Sleep, where the CPU external clock is also stopped, thus saving more power.

The way the CPU enters C3 state depends on the manufacturer. Intel CPUs add an extra pin, called SLP (or DPSLP, depending on the CPU model), which must be activated when the CPU is in C2 state in order to switch the CPU into C3 state. So first STPCLK pin must be activated and then one should activate the SLP pin. Entering the Deep Sleep state is achieved by simply cutting the external clock signal.

These transitions are the reason why you see stability gain out of turning them off, as they are playing with the clock and power input to the cpu.


C1E and Speedstep are both bundled together as they do nearly the same thing(couple posts back C1E seems to take over Speedstep duties if speedstep is shut down) you can kind of think of speedstep as C1E 2.0 as its essentially doing the same exact things to the cpu. C1E has idle and full load, speedstep has everything in between too. Windows doesnt implement speedstep properly however with out third party tools to help it along. Linux and i think OSX does and will step up the cpu speed until its 'fast enough'
Edited by ryuji - 2/5/12 at 2:34pm
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post #7116 of 10701
338

24 hrs!biggrin.gif Finally took a break from Skyrim/BF3 to fine-tune my 4.5Ghz OC. Looks pretty good if I might say so myself.
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post #7117 of 10701
L3zRf.png

idk what to say
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post #7118 of 10701
Hey munaim1, been a while since I've been in this thread, I believe thanks and congratulations are in order and then I have a general question for the thread.

First off congratulations on the Intel editor, you deserve it! thumb.gif Now last time I was in here I was preparing to have to reattain stability and your suggestions made a big difference. After testing many many combinations I found a big improvement by setting the PLL to 1.65v, this allowed me to cut at least 10mV off of my vcore. I also took your advice to do a longer final Prime blend test seeing as I am a 24/7 folder, and after verifying Prime stability for 40 hours I've been 24/7 stable (knock on wood). So thanks for the advice.

Now my question to the any who feel up to answering it in here is this: I'm about to be getting some new RAM and will be OCing the hell out of it and just wanted to know if there was anything that I might need to adjust that had slipped my mind. I know to adjust the vDIMM (I likely won't go above 1.6v) and timings obviously and know that I might have to increase my VCCIO a little bit if I go really high (2133MHz) but other than that are there any other settings that I should keep in mind that might possibly need to be adjusted for a 2x4GB kit that might go up to 2133MHz on an Asus mobo? Like for example I shouldn't have to expect to increase my vcore for just two DIMMs of high speed RAM should I?
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post #7119 of 10701
I don't think so.
VCCIO as you said will probably need a bit of a boost, but I can't see it affecting vcore. If it means anything (in terms of stress on the IMC), I didn't need to up VCore OR VCCIO going from 2x2GB to 4x4GB 1600MHz DIMMs (30 mins 1792 FFT stable on both).
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post #7120 of 10701
Quote:
Originally Posted by csm725 View Post

I don't think so.
VCCIO as you said will probably need a bit of a boost, but I can't see it affecting vcore. If it means anything (in terms of stress on the IMC), I didn't need to up VCore OR VCCIO going from 2x2GB to 4x4GB 1600MHz DIMMs (30 mins 1792 FFT stable on both).

vccio should only need to be adjusted if you are running the memory at higher speed then the IMC wants, its basically the equivalent in the p4 world of overvolting your NB. You try not to, but sometimes to get that really nice bus speed you had to give it a few points.. or in other cases a lot of points wink.gif (i used to run my X48 mobo at 2132 bus (533 fsb). That basically required water cooling on the NB with how much voltage i was giving it) my 925 chipset needed an ass whooping to get 300 fsb. got 4.5 ghz at 1.18v 300 fsb tho on a 570j

worst cpu yet on nb's i have touched was dothan... i think its why intel went IMC... my NB literally exploded audibly at 275 fsb 3 ghz with the heat sink running ice cold (almost literally, my cpu was at 0C)
Edited by ryuji - 2/6/12 at 7:17am
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