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post #21 of 29
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Quote:
Originally Posted by Blameless View Post
CPUs prior to the integration of the IMC use the FSB to connect the chipset to the CPU. Since everything was connected to the chipset (memory, AGP/PCI/PCI-E/DMI buses, other CPUs, all of it), the performance of this bus was often the determining factor in overall system performance.

There was obviously a clock generator that set the reference/base clock, but since the FSB was directly linked to it with a fixed ratio, there was almost never a reason to distinguish between the two, so FSB and reference clock became synonymous.

In modern CPUs, there is no front side bus. The memory connects directly to an on-die memory controller, and a separate bus (hypertransport, QPI, or DMI) connects the much simplified chipset to the CPU. On the newest CPUs, even the primary PCI-E bus is integrated. There is still a reference clock, but since it's not tied to any single bus, calling it the FSB is a fairly serious misnomer.

So we've gone from one pipe carrying all data, to different paths for most everything. The performance of the chipset to CPU connection has become much less of an issue now that memory traffic is independent of it.
OK. So while an older motherboard would resemble this diagram I found on Wikipedia:



A Sandy Bridge motherboard would look like this one I drew in Paint:



Is that the right placement for the Clock Generator?
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post #22 of 29
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post #23 of 29
Quote:
Originally Posted by Rokabud View Post
OK. So while an older motherboard would resemble this diagram I found on Wikipedia:



A Sandy Bridge motherboard would look like this one I drew in Paint:



Is that the right placement for the Clock Generator?
lol @ "irrelevant bus"

The buses are still relevant, they are just all independent, and have plenty of bandwidth for their tasks, for the most part.

For Sandy Bridge, the clock generator is actually on the CPU itself.

Also, the PCH is more of a southbridge than a northbridge. Even the older X58 isn't really a northbridge as much as a glorified QPI to PCI-E bridge.
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post #24 of 29
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Quote:
Originally Posted by Blameless View Post
lol @ "irrelevant bus"

The buses are still relevant, they are just all independent, and have plenty of bandwidth for their tasks, for the most part.

For Sandy Bridge, the clock generator is actually on the CPU itself.

Also, the PCH is more of a southbridge than a northbridge. Even the older X58 isn't really a northbridge as much as a glorified QPI to PCI-E bridge.
Ohh, so the north and south bridges don't exist in the same sense they used to?

All that hasn't been integrated to the CPU has been moved to this "PCH"?

So P67, for example, is a chipset, and PCH is a..chipset architecture? Like: 2500K is to Sandy Bridge as P67 is to PCH?

Thanks for all the help so far =D
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post #25 of 29
Quote:
Originally Posted by Rokabud View Post
Ohh, so the north and south bridges don't exist in the same sense they used to?

All that hasn't been integrated to the CPU has been moved to this "PCH"?

So P67, for example, is a chipset, and PCH is a..chipset architecture? Like: 2500K is to Sandy Bridge as P67 is to PCH?

Thanks for all the help so far =D
PCH is Platform Controller Hub; basically Intel's term for the current single-chip chipsets. The X58 was an IOH, or I/O Hub. The line of southbridges were/are the ICH, or I/O Controller Hub. Intel called it's northbridges (prior to their integration on the CPU) MCH, or Memory Controller Hub.

Sandy Bridge is a code name for a CPU architecture. Cougar Point is the code name for the P6x and H6x chipset architectures.

So, 2500k is to Sandy Bridge as P67 is to Cougar Point. Also 2500k is to CPU as P67 is to PCH.
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post #26 of 29
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Quote:
Originally Posted by Blameless View Post
PCH is Platform Controller Hub; basically Intel's term for the current single-chip chipsets. The X58 was an IOH, or I/O Hub. The line of southbridges were/are the ICH, or I/O Controller Hub. Intel called it's northbridges (prior to their integration on the CPU) MCH, or Memory Controller Hub.

Sandy Bridge is a code name for a CPU architecture. Cougar Point is the code name for the P6x and H6x chipset architectures.

So, 2500k is to Sandy Bridge as P67 is to Cougar Point. Also 2500k is to CPU as P67 is to PCH.
So, P67 is a single chip within a chipset- but in this case, the only one. And there used to be other chips for different functions, like this "X58"?

So PCH literally refers to the new chipset, but since there's only one it has a new name?

Also, what is the difference between the IOH and the ICH? Does the IOH contain the actual physical connectors on the I/O shield? Would the relationship between the IOH and the ICH be similar to that between the CPU and the clock generator? One component directs, the other operates accordingly?

Thanks so much for sticking with me =D
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post #27 of 29
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post #28 of 29
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post #29 of 29
Hi all, You can buy the Embedded system board integrated with microprocessors after visiting the following link..............Computer Parts
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