CPUs prior to the integration of the IMC use the FSB to connect the chipset to the CPU. Since everything was connected to the chipset (memory, AGP/PCI/PCI-E/DMI buses, other CPUs, all of it), the performance of this bus was often the determining factor in overall system performance.
There was obviously a clock generator that set the reference/base clock, but since the FSB was directly linked to it with a fixed ratio, there was almost never a reason to distinguish between the two, so FSB and reference clock became synonymous.
In modern CPUs, there is no front side bus. The memory connects directly to an on-die memory controller, and a separate bus (hypertransport, QPI, or DMI) connects the much simplified chipset to the CPU. On the newest CPUs, even the primary PCI-E bus is integrated. There is still a reference clock, but since it's not tied to any single bus, calling it the FSB is a fairly serious misnomer.
So we've gone from one pipe carrying all data, to different paths for most everything. The performance of the chipset to CPU connection has become much less of an issue now that memory traffic is independent of it.
A Sandy Bridge motherboard would look like this one I drew in Paint:
Is that the right placement for the Clock Generator?