Originally Posted by 1usmus
why do you have such low tRRDS, tRCDWR , tRTP , tFAW and too high tWR, tRDWR?
honestly I'm surprised they have stability
Hi 1usmus, thanks you for the reply.
I used your DRAM Calculator to give a starting point, but in your calculator for Micron E/H the max frequency is 3466Mhz. I stayed with that because anything higher would give errors in memtest.
So, because I couldn't go higher. I just started tightening the timings. Primary timing hold the best latency improvement as far as I know, so I started with tCL, tRCDWR, tRCDRD, tRP, tRAS and tRC.
tRCDWR surprised me the most by going all the way down to 10. Believe me, I checked for errors at 16, 14 and 12 as well.
tRAS was also surprising because it is so much lower even XMP.
As far as the secondary timings, I just started tightening timings to see if they offer any further performance compared to the timings provided by DRAM Calculator.
One question I have, maybe I just missed something. In my bios I have 2 parts for CAD Sub settings.
In the DRAM Calculator it doesn't provide any values for the first part below..
First part is: CAD Sub Timing Configuration. (these are all still on auto)
Second part is: CAD Sub Strength Configuration.
ClkDrvStren [20 ohm]
AddrCmdDrvStren [20 ohm]
CsOdtDrvStren [20 ohm]
CkeDrvStren [20 ohm]
What values would work best there?