Originally Posted by KedarWolf
I read at higher voltages too low proODT can hurt signal integrity. Why I keep it proODT at 43.6 and 40-20-20-24 CAD_BUS as someone suggested.
I have tried lower proODT though and never really had issues, as low as 34.4.
Run my RAM at 1.5v. VDDGs at .950, VDDP at .900v.
Should I try to run it at 34.4 again and how do I test if I have issues?
I'm so far stable at 43.6 etc. Gonna run HCI for a dozen hours or more overnight and while I'm at work.
The way memory OC on ryzen as general works is:
The higher procODT is, the worse signal integrity gets and playroom is less
(after 60-68/69 ohm , you can't push FCLK at all, on every ryzen)
But high procODT is required if you push high vSOC through it, or have high density kits
(which includes higher procODT to start with, SR 28-40ohm, DR 48-60ohm)
procODT range changes with AGESA and 1003ABBA rec lowest was 34.4 or sometimes 32, current rec is 28ohm with 24-20-20-24 but you can push the first value higher
24<->48-20-20-24 for SR, 60<->120-20-20-24 for DR or higher amount of kits with big capacity
^ source 1usmus, as always
My findings are, that you need to up CAD_BUS resistance if you go high with vDIMM too
Else yes you are right, high vSOC if needed, can have negative effects on the sillicon if procODT is too low
although, who would push 1.3v SOC with 20ohm proc
Sometimes board default to 1.2v , which defaults to 60ohm proc , and of course 1.1v VDDP&VDDG
defaulting to low vSOC is only possible with VDDP & VDDG are lower, because of the range
you can't lower vSOC under VDDG voltage, same as you can't lower VDDG under VDDP voltage