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post #3201 of 3348 (permalink) Old 03-25-2020, 08:46 PM
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Quote: Originally Posted by nick name View Post
Run Karhu overnight with CPU Cache set to Enabled under the Advanced tab. You don't want to run it that way while using anything else though as the cache testing slows everything down.
I prefer HCI MemTest Pro with the threads allocated script to run it I've shared.

I find it'll find errors Karhu can miss.

Here's an hour of Karhu. Gonna run HCI 7 hours overnight plus several hours while at work tomorrow.




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post #3202 of 3348 (permalink) Old 03-25-2020, 09:02 PM
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Quote: Originally Posted by rares495 View Post
@Veii tRFC 234 is not stable at all and can't post with lower than 10 tRDWR. Sadly I do not have the time to play around anymore right now but will continue to push tonight.

Current settings:

VDDP 0.900V
VDDGs 0.950V
procODT & all that stuff = Auto (didn't even have to scroll so far down in the bios for these results - might have to do it to go lower)
34.4Ω and 28Ω is your procODT range
(lower = better, but works together with CAD_BUS, vCore & vSOC,
less voltage, less resistance needed=cleaner signal integrity=higher potential FCLK)

lowest vSOC = 1.0v (minimum 50mV higher than VDDG, optimally 75mV higher)
CAD_BUS depends on AGESA
on one hand 24-24-24-24 does work
on the other hand 30-20-20-24 does work better
Even 40-20-20-24 should work well for you on higher voltages
(higher voltage, higher resistance, higher drivestrengh)
Quote: Originally Posted by Veii View Post
Quote:
Translated from @cm87 very helpful RAM OC PDF Guide posted on Hardwareluxx
About the CAD-Values:
• CLKDrvStr - Helpful gainst Post Problems with low ProcODT (recommendation less Ω)
• AddrCmdDrvStr - Does influence stability quite a bit (recommendation 30 or higher - find it out single handed)
• CsOdtDrvStr - It's quite similar to how RTT_NOM works (try out what runs better - to be known, higher values increase the chance of POST issues)
• CKEDrvStr - against waking up from sleep issues (more is better, but does increase thermals by quite a bit)
Yes tRFC lowest mentioned is for perfect sync, something likely still overshoots
tRDWR goes together with tWRRD in steps
Here it was re-replained and rephrased, hopefully understandable this time
EDIT: i think i found the issue
Try tWR 13, or 9
~ tho you overshoot somewhere with delay to not having it post

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post #3203 of 3348 (permalink) Old 03-25-2020, 09:04 PM
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Quote: Originally Posted by Veii View Post
34.4Ω and 28Ω is your procODT range
(lower = better, but works together with CAD_BUS, vCore & vSOC / less voltage, less resistance needed=cleaner signal integrity)
lowest vSOC = 1.0v (minimum 50mV higher than VDDG, optimally 75mV higher)
CAD_BUS depends on AGESA
on one hand 24-24-24-24 does work
on the other hand 30-20-20-24 does work better
Even 40-20-20-24 should work well for you on higher voltages
Yes tRFC lowest mentioned is for perfect sync, something likely still overshoots
tRDWR goes together with tWRRD in steps
Here it was re-replained and rephrased, hopefully understandable this time
Thanks. I'll give it a try tonight.

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post #3204 of 3348 (permalink) Old 03-25-2020, 09:17 PM
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Quote: Originally Posted by Veii View Post
34.4Ω and 28Ω is your procODT range
(lower = better, but works together with CAD_BUS, vCore & vSOC / less voltage, less resistance needed=cleaner signal integrity)
lowest vSOC = 1.0v (minimum 50mV higher than VDDG, optimally 75mV higher)
CAD_BUS depends on AGESA
on one hand 24-24-24-24 does work
on the other hand 30-20-20-24 does work better
Even 40-20-20-24 should work well for you on higher voltages
Yes tRFC lowest mentioned is for perfect sync, something likely still overshoots
tRDWR goes together with tWRRD in steps
Here it was re-replained and rephrased, hopefully understandable this time
I read at higher voltages too low proODT can hurt signal integrity. Why I keep it proODT at 43.6 and 40-20-20-24 CAD_BUS as someone suggested.

I have tried lower proODT though and never really had issues, as low as 34.4.

Run my RAM at 1.5v. VDDGs at .950, VDDP at .900v.

Should I try to run it at 34.4 again and how do I test if I have issues?

I'm so far stable at 43.6 etc. Gonna run HCI for a dozen hours or more overnight and while I'm at work.




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post #3205 of 3348 (permalink) Old 03-25-2020, 09:33 PM
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Quote: Originally Posted by KedarWolf View Post
I read at higher voltages too low proODT can hurt signal integrity. Why I keep it proODT at 43.6 and 40-20-20-24 CAD_BUS as someone suggested.

I have tried lower proODT though and never really had issues, as low as 34.4.

Run my RAM at 1.5v. VDDGs at .950, VDDP at .900v.

Should I try to run it at 34.4 again and how do I test if I have issues?

I'm so far stable at 43.6 etc. Gonna run HCI for a dozen hours or more overnight and while I'm at work.

Spoiler!
The way memory OC on ryzen as general works is:
The higher procODT is, the worse signal integrity gets and playroom is less
(after 60-68/69 ohm , you can't push FCLK at all, on every ryzen)
But high procODT is required if you push high vSOC through it, or have high density kits
(which includes higher procODT to start with, SR 28-40ohm, DR 48-60ohm)
procODT range changes with AGESA and 1003ABBA rec lowest was 34.4 or sometimes 32, current rec is 28ohm with 24-20-20-24 but you can push the first value higher
24<->48-20-20-24 for SR, 60<->120-20-20-24 for DR or higher amount of kits with big capacity
^ source 1usmus, as always

My findings are, that you need to up CAD_BUS resistance if you go high with vDIMM too
Else yes you are right, high vSOC if needed, can have negative effects on the sillicon if procODT is too low
although, who would push 1.3v SOC with 20ohm proc
Sometimes board default to 1.2v , which defaults to 60ohm proc , and of course 1.1v VDDP&VDDG
defaulting to low vSOC is only possible with VDDP & VDDG are lower, because of the range
you can't lower vSOC under VDDG voltage, same as you can't lower VDDG under VDDP voltage

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post #3206 of 3348 (permalink) Old 03-25-2020, 10:49 PM
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Currently running G-SKILL DDR4-3000 CL14. It's B-die but it seems to be of a lower quality. I'm getting errors shortly after starting the memtest. Have no idea where to start looking. I was going to try the SAFE preset since it doesn't change much but I haven't gotten around to doing that yet.

I'm using 1USmus's FAST profile for dual rank with timings pictured below. I noticed the timings somehow changed, magically, on their own, when I ran the AIDA memory benchmark again. Doesn't seem to have cost me any performance but wierd. Dram voltage is at the recommended 1.35. Do I need to turn it up to get passed these errors? Thanks!
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post #3207 of 3348 (permalink) Old 03-25-2020, 11:08 PM
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Quote: Originally Posted by Tobiman View Post
Currently running G-SKILL DDR4-3000 CL14. It's B-die but it seems to be of a lower quality. I'm getting errors shortly after starting the memtest. Have no idea where to start looking. I was going to try the SAFE preset since it doesn't change much but I haven't gotten around to doing that yet.

I'm using 1USmus's FAST profile for dual rank with timings pictured below. I noticed the timings somehow changed, magically, on their own, when I ran the AIDA memory benchmark again. Doesn't seem to have cost me any performance but wierd. Dram voltage is at the recommended 1.35. Do I need to turn it up to get passed these errors? Thanks!
tRC should be equal to tRAS + tRP => 16-16-16(tRP)-36(tRAS)-52(tRC)

tFAW should be 4x tRRDS/tRRDL => 4/4 & 16

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post #3208 of 3348 (permalink) Old 03-25-2020, 11:13 PM
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Quote: Originally Posted by rares495 View Post
tRC should be equal to tRAS + tRP => 16-16-16(tRP)-36(tRAS)-52(tRC)

tFAW should be 4x tRRDS/tRRDL => 4/4 & 16
I fixed it. Still getting errors in membench though.
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post #3209 of 3348 (permalink) Old 03-25-2020, 11:16 PM
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Quote: Originally Posted by Tobiman View Post
I fixed it. Still getting errors in membench though.
You literally didn't apply a single setting I posted lol.

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post #3210 of 3348 (permalink) Old 03-25-2020, 11:21 PM
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Quote: Originally Posted by rares495 View Post
You literally didn't apply a single setting I posted lol.
I'll do so now.
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