Originally Posted by Tobiman
I fixed it. Still getting errors in membench though.
Originally Posted by rares495
You literally didn't apply a single setting I posted lol.
tRRDS to tFAW doesn't have to be *4
It can be *4 for tightest, *5 for common, *6 for failsafe, 6*6 36 tFAW, nothing wrong
but what IS WRONG, are his tRDWR & tWRRD settings
Before when he/she had SLC 4, 16-16-16-25 , 8/4 did work, although 8/1 would work
4*4 16 tRCDRD , 8*2 16 tRCDWR, covering it perfectly
BUT - now he has SLC 5 inside
tRDWR isn't bothered by that, can still use tRDWR 8 or 9
But if he uses 8 and his kits require this delay bump - tWRRD should be 3=3*5 15 , 4*5=20 which overshoots tRCDRD
Not always will tRRDS *4 work, especially since this looks like dual rank kits
Although to your defense rares,
didn't attach any Thaiphoon burner report showing IC size in nm, rank density and showing PCB layout if (A0,A1,A2 or B0,B1,B2)
Soo we are working here blind
Originally Posted by KedarWolf
Is there a website that has ALL the timing rules for the Ryzen 3*** series?
Ryzen has the same settings since gen 1, same rules only ranges differ and CAD_BUS,RTT,procODT differs between bios and ICs
This was my guide of explaining, although i did post it one page back on here
and this is the page you might be looking for, but it doesn't cover the rules
After all, there are nearly no public rules - simply as they are many ways of calculation
Only first 3 timings change freely without rulesets: tCL, tRCD, tRP
They differ between ICs and depend on more than just "delay"
Don't forget, 3rd gen does autocorrect timings,
A passed set of timings ≠ a good set of timings
Boards do autoinject delay since gen 1 , tiny bit but you'll notice it on SiSandra results