[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread - Page 322 - Overclock.net - An Overclocking Community
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[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

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post #3211 of 3348 (permalink) Old 03-26-2020, 12:34 AM
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Quote: Originally Posted by Tobiman View Post
I'll do so now.

Up the voltage to 1.45v first, then you can tune it down once you're stable.
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post #3212 of 3348 (permalink) Old 03-26-2020, 02:50 AM
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Quote: Originally Posted by rares495 View Post
tRC should be equal to tRAS + tRP => 16-16-16(tRP)-36(tRAS)-52(tRC)

tFAW should be 4x tRRDS/tRRDL => 4/4 & 16
Is there a website that has ALL the timing rules for the Ryzen 3*** series?

I know I had a website for Intel.

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post #3213 of 3348 (permalink) Old 03-26-2020, 02:55 AM
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Quote: Originally Posted by nick name View Post
I haven't seen you post any test results. Do you test for stability?
Goin to let it run at least another 10 hours or so while I'm at work.

Been going 5.5 hours as is.


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post #3214 of 3348 (permalink) Old 03-26-2020, 05:00 AM
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@Veii Can you give me some guidance. I can't seem to run anything lower than tRFC 310 and maintain an error free Karhu test. And I can run tRTP at 8 with tRFC of 310 for 9 hours error free.
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post #3215 of 3348 (permalink) Old 03-26-2020, 07:51 AM
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Quote: Originally Posted by Tobiman View Post
I fixed it. Still getting errors in membench though.

Quote: Originally Posted by rares495 View Post
You literally didn't apply a single setting I posted lol.
tRRDS to tFAW doesn't have to be *4
It can be *4 for tightest, *5 for common, *6 for failsafe, 6*6 36 tFAW, nothing wrong
but what IS WRONG, are his tRDWR & tWRRD settings
Before when he/she had SLC 4, 16-16-16-25 , 8/4 did work, although 8/1 would work
4*4 16 tRCDRD , 8*2 16 tRCDWR, covering it perfectly
BUT - now he has SLC 5 inside
tRDWR isn't bothered by that, can still use tRDWR 8 or 9
But if he uses 8 and his kits require this delay bump - tWRRD should be 3=3*5 15 , 4*5=20 which overshoots tRCDRD

Not always will tRRDS *4 work, especially since this looks like dual rank kits
Although to your defense rares, @Tobiman didn't attach any Thaiphoon burner report showing IC size in nm, rank density and showing PCB layout if (A0,A1,A2 or B0,B1,B2)
Soo we are working here blind

Quote: Originally Posted by KedarWolf View Post
Is there a website that has ALL the timing rules for the Ryzen 3*** series?
Ryzen has the same settings since gen 1, same rules only ranges differ and CAD_BUS,RTT,procODT differs between bios and ICs
This was my guide of explaining, although i did post it one page back on here
https://www.overclock.net/forum/11-a...l#post28246564
and this is the page you might be looking for, but it doesn't cover the rules
https://reddit.com/r/overclocking/co...g_on_ryzen_oc/
After all, there are nearly no public rules - simply as they are many ways of calculation
Only first 3 timings change freely without rulesets: tCL, tRCD, tRP
They differ between ICs and depend on more than just "delay"

Don't forget, 3rd gen does autocorrect timings,
A passed set of timings ≠ a good set of timings
Boards do autoinject delay since gen 1 , tiny bit but you'll notice it on SiSandra results

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post #3216 of 3348 (permalink) Old 03-26-2020, 08:06 AM
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@Veii I could have just quoted you, of course. Perhaps I'll do that next time.

Can you explain the SLC thing?

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post #3217 of 3348 (permalink) Old 03-26-2020, 08:20 AM
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Quote: Originally Posted by nick name View Post
@Veii Can you give me some guidance. I can't seem to run anything lower than tRFC 310 and maintain an error free Karhu test. And I can run tRTP at 8 with tRFC of 310 for 9 hours error free.
14-14-16-14-30-54
tRFC 378-281-173 or 324-241-148
SCL 3
tRDWR 8
tWRRD 4
tRTP is 9 or 6 (for 324 tRFC)
1.46vDimm ~ till we get a thaiphoon burner report from you

used tRDRD / tWRWR SD & DD values of 4,4-6,6 don't always deliver better performance
same as tRDDS, tRDDL 4,4 are not always better than 4,6
You can use 4,5 if you want
As you used GDM , every odd value will be even , you are running 14-14-16 in reality

The best you could do is either get GDM away, or lower tRC-2 at the end to tRC 52,
which would make 312-232-143 (164.22ns) with tRTP of 6,8,12 as option to select
that turns tWR as 12 or 8

Here some more rules:

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post #3218 of 3348 (permalink) Old 03-26-2020, 08:29 AM
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Quote: Originally Posted by rares495 View Post
@Veii I could have just quoted you, of course. Perhaps I'll do that next time.

Can you explain the SLC thing?
SCL as alone SCL, not 100%
it has more connections to it - but ultimately it depends on PCB layout (trace layout) and current sensing unit (voltage+free voltage after tRP precacharge)
And it can be used for tWRRD calculation - if you need on odd values like tRCD 17 to calculate tRDWR
(that would be 9 which has remain unused delay, or 8 which needs then a bit of latency added from tWRRD, to compensate - but would give a faster bandwidth boost)
I often used it for CL14 flat - while taking tRDWR 6,3 instead of 7,1 / 3 because SLC was 2, but it would've worked borderline on SCL 3 too as 3*4 12 instead of 14 ~ key is to not overshoot

SCL is not only PCB related but also frequency related
this is a tiny illustration of some of the ranges, although it's a flawed one without any delay used
SCL is strange on it's own - same as both SD DD values are not fully clear how to calculate
I need to get the exact cycle times correct of how memory behaves
That way get "world clock" delay, and so let me adjust perfect tRFC and automate every timing at the end (then i'll release the full manual calculator)
But all that is still wip for couple more weeks , later when i get this result finally - i will automate everything and work with "timing efficiency" not only "high bandwidth and calculated timing latency"
* we know, 3467CL12 is faster than 3600C14

EDIT:
The only advice i can give is
In order to lower SCL, you need everything lower - including low tRFC
too high tRFC and low SCL won't be stable

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Last edited by Veii; 03-26-2020 at 08:49 AM.
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post #3219 of 3348 (permalink) Old 03-26-2020, 08:46 AM
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Quote: Originally Posted by Veii View Post
14-14-16-14-30-54
tRFC 378-281-173 or 324-241-148
SCL 3
tRDWR 8
tWRRD 4
tRTP is 9 or 6 (for 324 tRFC)
1.46vDimm ~ till we get a thaiphoon burner report from you

used tRDRD / tWRWR SD & DD values of 4,4-6,6 don't always deliver better performance
same as tRDDS, tRDDL 4,4 are not always better than 4,6
You can use 4,5 if you want
As you used GDM , every odd value will be even , you are running 14-14-16 in reality

The best you could do is either get GDM away, or lower tRC-2 at the end to tRC 52,
which would make 312-232-143 (164.22ns) with tRTP of 6,8,12 as option to select
that turns tWR as 12 or 8

Here some more rules:
Sorry, I'm running a G.Skill 3600C15 b-die kit.

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post #3220 of 3348 (permalink) Old 03-26-2020, 08:50 AM
Stock is too casual~
 
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Quote: Originally Posted by nick name View Post
Sorry, I'm running a G.Skill 3600C15 b-die kit.
Thaiphoon burner readout please
Even from the same model number, you can have two different PCB revisions
and different b-die nm sizes

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