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post #4251 of 4457 (permalink) Old 08-01-2020, 02:36 PM
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Quote: Originally Posted by Gadfly View Post
do it in another thread. This is supposed to help people find and compare stable results.
If you want another thread then start another thread. Being able to compare failures and successes seems useful to me.

I'm not sure exactly when people stopped following the guidelines that Silent Scone set, but it was a good while ago.

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post #4252 of 4457 (permalink) Old 08-01-2020, 03:18 PM
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Quote: Originally Posted by chitos123 View Post
https://docs.google.com/spreadsheets...gid=1439155382


Please test my calculator
And tell me, any mistake or wrong calculation
Ooh new spreadsheets tot play with. Very Nice Veii. Bought a 32gb dual ranked kit but one dimm was faulty. Will test your calc when the replacement kit arrives!
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post #4253 of 4457 (permalink) Old 08-01-2020, 03:47 PM
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Quote: Originally Posted by Eder View Post
Ooh new spreadsheets tot play with. Very Nice Veii. Bought a 32gb dual ranked kit but one dimm was faulty. Will test your calc when the replacement kit arrives!
Wrong person, he/she did it all by himself
Unless you mean this little cutout with the boxes on the quote ?
But this thing exists far before tRFC mini was published - it was taken from this bigger project, to help people as it was needed
It's rough and not useful the docs screenshot

@chitos123 did good work ~ it just looks a bit complex to use, but this comes by time
Oh you did also a wonderful job this page http://cooln.kr/bbs/37/224005
If you ever publish it on twitter, please let me retweet it

@Eder , this cutout what you see is being on hold since long time
Too long tbh, but priority had a mobile app before this huge thing is published
It's goal is actual simulation prediction - prediction how autocorrect will work and simulate "timing efficiency" between clocks
So far it's not sharable, it's not better than chitos - chitos did very good and not all rulesets exist
SD, DD needs a strickt research and SCL needs a very strict research , same as tWTR_ range
~ all up to PCB

The rest pretty much is solid and calculable
tRFC part needs further research to drop lower than *6 and calculate tSTAG without user readout
tREFI calculation misses and we AMD users need access to that value - without auto calculation
Quote: Originally Posted by mongoled View Post
So experimenting with values I have never tried before.
I got two completed runs (1st run passed, reboot, 2nd run passed) with the same settings as in screen shot below, but with tRP at 14.

But did not really see any performance benefits from the settings in my sig.
Dropping tRP to 12 clearly brought better performance, though I now have two new errrors.

Error 14,which Veii has explained as
But ive never come across an explanation for error 9.

Id love to get this stable, looks to be alot closer to stabilty than trying to run tRCDRD at 14!
Would increaing ClkDrvStrength help with these types of error as i have it set to 20 ohms .....
Error 14 we know is MirrorMove 0mb, a timeout issue
Error 9 burst test 4mb is a voltage stability issue
If you've lowered tRP , increase vDimm a tiny bit
If you've increased tRP to longer delay, decrease vDIMM +0.01 , one tiny step

14 remains a timeout issue, but the pattern shows
First it chokes, then it can't (p)recharge in time the cells
soo first fix your timeout issue, later maybe the voltage will be fine for it
But by time heat will increase, cells will faster discharge and you'll get the same error 9 again
First fix Error 14

Try if tRTP 8 fixes it
If not, use tRRD_L 5
if you still choke at the same time, push tWTR_L to 10
And if you still have the issues,well increase vDIMM as tRP is too low at 12
tRP 12 or tRP 14 shouldn't matter, tRC can go down to -2 on Single rank without feeling negative effects
Only tRAS has to be perfectly accurate
tRP scales by temperature and tRCD, but voltage dominates ~ it's all just discharge prediction at this point

... i actually see an issue
tCL 14 + tWR 10 + tBL 2 = 26
28 might be too long for tRAS,
What will happen if you just change tRP to 14 and tRAS to 26 ~ without any other changes ?

EDIT:
@chitos123
Quote:
tRFC 는 고정값이 아닙니다, 클린한 리프레시 사이클을 나타내는데 주로 사용되며
충전이 끝나기 전, 시간에 맟춰 행을 활성화 시킵니다

하지만 메모리는 타임 브레이크(Time-Break) 능력이 있으며, 또한 모든 규칙을 무시할 수 있습니다

tRFC 는 이중 하나이며,시간에 맞춰 수동으로 작동되기도 하고, 자동으로 우회하여 필요할때 작동되기도 합니다

낮은 tRFC 값, 혹은 제가말하는 "동기화 되지 않은 값은" 성능을 떨어 뜨릴수 있습니다
높은값도 동일합니다(너무 높을수 있습니다)
Auto-Translated:
Spoiler!

This likely was the talk with Gadfly and me
There is a missunderstanding coming from Intel way of OC and AMD way
Intel users have no tRC and use tRAS plus tRFC + tREFI ~ missunderstandings happen

tRFC is a fixed delay value,
tRC is also a fixed delay but a variable=scale-able (only tRAS is not scale-able, tRP adapts)
tRFC is a repeating refresh cycle a whole cycle inside tREFI range

It will happen and it will stay active till it happens, till it expires
If it happens not fast enough "too late" , it will be postponed up to 9* inside the whole tREFI range
tREFI is calculated by tRFC1-2-4 all 3 of them

Accuracy of tRFC remains important when you want a clean transition
if tRFC is too low, it will try to postpone, timebreak and repeat it self
if tRFC is too high , it will wait till it elapses, stop everything else and wait for it to finish

tREFI range on AMD depends if memory clear is enabled or disabled
Recommended is Disabled, soo whole tREFI range will pass and no early random refresh happens
Memory will break tRFC rule if tRFC 2 or 4 is awkward, but it's a fixed delay and it will stay on it till this delay elapses
Same characteristics for tRC

tRC has to finish before anything else can be done
You can abuse this a bit and lower it - the same way 1usmus knows a method to lower tRFC even further by using tSTAG
But every timing we can change are fixed delays
The rest are identical amount of realtime autocorrecting timings which adapt by the accuracy of the fixed delays
tMRD state and tMOD are one of them - tRFC whole set a -1/+1 rounding will mess up autocorrecting values, readable via old RTC and current 1.0.0.8 ZenTimings

In the future i hope that we can readout all autocorrecting timings including tAL on each primary
But this is a project in the future and an issue which needs to be resolved before Renoir fully launches
Let's say before consumer 4xxx launches with variable MCLK, FCLK, UCLK

EDIT 2:
tRFC will only be postponed if tRAS happened, Data was transferred to sensing amp, tRP tried to (p)recharge, tRC killed this cycle too early
tRFC will try to trigger with the same delay of tRAS+tRP multiple times , but after a point discharge happens too fast and it can't keep up. Then tRFC is postponed to another time after tRC ends again(the next cycle)
Little cheat-sheet
Spoiler!

EDIT 3:
4.) in the writeup is very valuable, i understand my mistake and will need to retest and readjust the ruleset of tRAS & tRC
Haven't seen negative effects by going that high , but 14-14-14 making min tRAS=16 not 28 is a too big difference to ignore
Thank you again for collecting both sides of the learning experience. You never can learn enough. 1usmus explanation makes perfect sense
Quote:
tRAS, Min = tRCD + tCL + (tBL-(tCL-1))-1
= tRCD+tBL = tRCD +2

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post #4254 of 4457 (permalink) Old 08-01-2020, 11:12 PM
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Quote: Originally Posted by veii
Error 14 we know is MirrorMove 0mb, a timeout issue
Error 9 burst test 4mb is a voltage stability issue
If you've lowered tRP , increase vDimm a tiny bit
If you've increased tRP to longer delay, decrease vDIMM +0.01 , one tiny step

14 remains a timeout issue, but the pattern shows
First it chokes, then it can't (p)recharge in time the cells
soo first fix your timeout issue, later maybe the voltage will be fine for it
But by time heat will increase, cells will faster discharge and you'll get the same error 9 again
First fix Error 14

Try if tRTP 8 fixes it
If not, use tRRD_L 5
if you still choke at the same time, push tWTR_L to 10
And if you still have the issues,well increase vDIMM as tRP is too low at 12
tRP 12 or tRP 14 shouldn't matter, tRC can go down to -2 on Single rank without feeling negative effects
Only tRAS has to be perfectly accurate
tRP scales by temperature and tRCD, but voltage dominates ~ it's all just discharge prediction at this point

... i actually see an issue
tCL 14 + tWR 10 + tBL 2 = 26
28 might be too long for tRAS,
What will happen if you just change tRP to 14 and tRAS to 26 ~ without any other changes ?
Thank you for the explanation, I will try some of those things out.

FYI,

I simply increased ClkDrvStrength from 20 ohms to 24 ohms and ran TM5, this time I had no error 9 or 14, but only one error that was 11.

Am going to reboot and re-run TM5 to see if its repeatable.

** EDIT **
2nd run had 5 errors in test 1

Going to re-run the settings that got me 9 & 14 errors to see if its reproducable, need to confirm that increasing ClkDrvStength is shifting where the errors are produced ...

** EDIT2 **
Ughhh, scratch the repeatable testing, once I changed some values in RM, max volts RM applies to vDIMM is 1.5v, I need 1.52v and since I am running these tests remotely, I will need to continue this when i am at the office

:\

This seems similar to what rares was seeing in April when he was playing with getting tRP stable at 12....

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post #4255 of 4457 (permalink) Old 08-01-2020, 11:19 PM
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Quote: Originally Posted by mongoled View Post
Thank you for the explanation, I will try some of those things out.

FYI,

I simply increased ClkDrvStrength from 20 ohms to 24 ohms and ran TM5, this time I had no error 9 or 14, but only one error that was 11.

Am going to reboot and re-run TM5 to see if its repeatable.

This seems similar to what rares was seeing in April when he was playing with getting tRP stable at 12....
Never seen errors 9 & 14. Never seen anyone else get them. Could this be related to your high BCLK? By the way, why are you not back to 100? Does it allow for higher CPU OC or something?

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post #4256 of 4457 (permalink) Old 08-01-2020, 11:27 PM
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Quote: Originally Posted by rares495 View Post
Never seen errors 9 & 14. Never seen anyone else get them. Could this be related to your high BCLK? By the way, why are you not back to 100? Does it allow for higher CPU OC or something?
Yes, you did not have 9 & 14, but you were alternating between other batches of error codes

https://www.overclock.net/forum/10-a...l#post28408882 (only reference I found veii talk about error 9)



Yeah, nice boost speeds that are "automated" dependant on load,

Example TM5 runs 4500+ all core.

Prime95 runs 4380+ all core

Single core boosts 4600+

Ive done loads of testing when I was trying to work out those weird issues I was having 10 days ago.

BCLK or high boost clocks was never the culprit, was just for some reason I needed slighly more vDIMM as in compared to what i previously stable ....

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post #4257 of 4457 (permalink) Old 08-01-2020, 11:55 PM
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Quote: Originally Posted by mongoled View Post
Yes, you did not have 9 & 14, but you were alternating between other batches of error codes

https://www.overclock.net/forum/10-a...l#post28408882 (only reference I found veii talk about error 9)



Yeah, nice boost speeds that are "automated" dependant on load,

Example TM5 runs 4500+ all core.

Prime95 runs 4380+ all core

Single core boosts 4600+

Ive done loads of testing when I was trying to work out those weird issues I was having 10 days ago.

BCLK or high boost clocks was never the culprit, was just for some reason I needed slighly more vDIMM as in compared to what i previously stable ....
So are you at 1.5V VDIMM yet?

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post #4258 of 4457 (permalink) Old 08-02-2020, 12:54 AM
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1.52v in BIOS, reads 1.536v in HWInfo64



** EDIT **
OK, looks like ive worked out the reason the required vDIMM changes, but do not know why it happens.

So I just finished a TM5 25 cycles with Veii suggestion of using tRAS @26.

It completed with no errors, however, I was looking at the load vDIMM and instead of being 1.536v it was @1.552v occasionaly dropping to 1.536v.

So it seems the vDIMM voltage is not a constant on each different reboot.

At least according to what HWInfo64 is relaying.

Ive now set in the BIOS 1.51v and now HWInfo64 is showing a steady 1.536v under load, hopefully this will pass the 25 cycle test and than will have to reboot and run it again just to make sure ...

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post #4259 of 4457 (permalink) Old 08-02-2020, 07:25 AM
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Quote: Originally Posted by mongoled View Post
1.52v in BIOS, reads 1.536v in HWInfo64



** EDIT **
OK, looks like ive worked out the reason the required vDIMM changes, but do not know why it happens.

So I just finished a TM5 25 cycles with Veii suggestion of using tRAS @26.

It completed with no errors, however, I was looking at the load vDIMM and instead of being 1.536v it was @1.552v occasionaly dropping to 1.536v.

So it seems the vDIMM voltage is not a constant on each different reboot.

At least according to what HWInfo64 is relaying.

Ive now set in the BIOS 1.51v and now HWInfo64 is showing a steady 1.536v under load, hopefully this will pass the 25 cycle test and than will have to reboot and run it again just to make sure ...
I guess it's board (and BIOS) dependent as I see a droop in HWiNFO. Setting 1.5V droops down to ~1.48V and does not go higher than what is set. This isn't a behavior I remember from the period I was using my 2700X on the board, however.

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post #4260 of 4457 (permalink) Old 08-02-2020, 08:51 AM
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Zen Timings 1.0.8 released.

https://github.com/irusanov/ZenTimings/releases

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