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post #4251 of 4271 (permalink) Old 08-04-2019, 03:33 PM
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Quote: Originally Posted by adam3234 View Post
What do you guys think are the chances that the next Threadripper generation(s) and their mother boards will support 16 ram slots and octo channel memory? I would like an extra 128 GB of RAM. I heard there was going to be a big drops in RAM prices (something like up to 42.1%) and was thinking it'll be a good time to buy more RAM if future Threadrippers motherboards will support more RAM slots...hmm...will those mother boards even have the room for the extra RAM slots?
Better buy your RAM now. Prices are going back up since all the manufacturers are reducing wafer starts to reduce the glut of memory in the distribution channel so that they can recover average selling prices for dies.

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post #4252 of 4271 (permalink) Old 08-04-2019, 05:41 PM
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Quote: Originally Posted by Keith Myers View Post
Better buy your RAM now. Prices are going back up since all the manufacturers are reducing wafer starts to reduce the glut of memory in the distribution channel so that they can recover average selling prices for dies.
Not only that, chemicals used to make the wafers are going up in cost due to a trade fight between Japan and S. Korea. So even if they reduced production, there is also the cost of manufacturing that is rising.

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post #4253 of 4271 (permalink) Old 08-05-2019, 02:57 AM
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Quote: Originally Posted by ajc9988 View Post
... there is little reason for AMD to move the 8-channel to HEDT at this moment...
I was hoping new 4 die Threadripper CPUs will encourage AMD to upgrade the tr4 socket to support 8 channels because without 8 channels 2 of the 4 dies that don't have direct RAM access will take a massive latency hit from having to request for RAM data from the other 2 dies with direct access to RAM...although that is with the Zen 1 architecture, I'm not sure how the Zen 2 architecture with it's chiplets and IO die architecture will handle memory requests from 4 dies.



Quote: Originally Posted by ajc9988 View Post
...Further, unless they planned on the forced upgrade of the socket, I don't really see this happening. The old X399 boards are not laid out for 8-channel, to my knowledge. So, if they wanted backwards compatibility, that would be out of the question....
I was hoping future boards like x699 or x799 etc will support 8 channels not AMD upgrading x399 boards to support 8 channels...although if AMD can do that then that will be pretty cool...although what I want is 16 slots and 8 channel support.
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post #4254 of 4271 (permalink) Old 08-05-2019, 03:35 PM
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Quote: Originally Posted by adam3234 View Post
I was hoping new 4 die Threadripper CPUs will encourage AMD to upgrade the tr4 socket to support 8 channels because without 8 channels 2 of the 4 dies that don't have direct RAM access will take a massive latency hit from having to request for RAM data from the other 2 dies with direct access to RAM...although that is with the Zen 1 architecture, I'm not sure how the Zen 2 architecture with it's chiplets and IO die architecture will handle memory requests from 4 dies.





I was hoping future boards like x699 or x799 etc will support 8 channels not AMD upgrading x399 boards to support 8 channels...although if AMD can do that then that will be pretty cool...although what I want is 16 slots and 8 channel support.
The I/O die centralizes ALL memory channels. All traffic going from one CCX to another, or to memory, goes to the I/O die. All latency was equalized in this way to address the issue of stale data. Windows also changed the scheduler so that the thread assigned is used and other threads are spawned on the same CCX until the CCX is full, then it goes to another CCX. Because the memory channels are centralized, it is the same latency to go the memory REGARDLESS of which core is requesting the information.

Further, your statement is predicated under the argument that the problem was memory bandwidth to the cores and NOT the latency causing stale data. Sure, memory bandwidth per core is going to be stretched a bit, except that all cores have equal access through a two hop solution, 1 hop to the I/O and 1 hop to the memory.

Now, AMD did this because the MS NUMA awareness was shiite. Meaning whenever it was in a NUMA situation, it allowed spawning to ONLY 1 extra node, meaning two of the four dies on the 2990WX. With a centralized I/O, the system recognizes the entire CPU as UMA, meaning one mem controller and die, roughly, rather than each die being a separate NUMA node, for simplicity sake. That means that the problem with NUMA has been resolved. And by standardizing all latency, even though it increased latency in some cases, it lowers the amount of stale data and other issues, thereby overall making the CPU faster. Efficiency through inefficiency.

So the problems of TR and TR second gen are gone. That also means that the new 32 cores will likely smash the crap out of the 18-core Intel CPUs and go toe to toe with the 28-core in many cases. Meanwhile, the 64-core variant, expected to be priced at $3000-3400, will be in the price category of the 28-core OC Xeon, while also beating it badly.

AMD is already said to be keeping backwards compatibility on the new third gen chips. Making those chips shut down two mem controllers with 2 channels per controller would be a PITA! I suppose it is possible, just very unlikely.

Instead, the new MBs will support PCIe 4.0. No new socket is likely until 2021 with DDR5 introduction. So chances of adding those memory lanes until then is small. Before they mentioned possible X399 compatibility, I was hoping, since we got two generations on the platform, for a potential new socket and additional lanes. But not happening is the most likely outcome.

As I believe I said, Intel isn't increasing their mem channels either. So that leaves little reason for complaint.

Finally, if you are going off of people saying their isn't enough bandwidth to run 32 cores on 4 channels of memory, that is FALSE. It was disproved when the scheduler part was shown. I, on my own, suspected a stale data problem for the cores without mem channels, as they were ALWAYS with the largest latency possible (there are 4 different latencies for core to core comms and two on memory, 1)same CCX, 2) different CCX on the same die, 3) mirrored CCX on a different die, and 4) different CCX on a different die; memory - 1) local memory controller, 2) memory controller on other die). So, you would wind up with the two dies without memory controllers always having to go off die for memory calls, while also having very long latencies on die to die comms, resulting in a lot of latency. Combine that with a scheduler acting opportunistically causing thread thrashing by moving apps to and from core 0 regularly, and you result in a system that is FUBARed in many use cases.

So, with Zen 2, you have two CPU comm latencies: 1) on same CCX, and 2) CCX to CCX. Further, you only have 1 memory latency, going to I/O, then going to memory. In addition, by centralizing the mem controller, the OS reads it as a single memory node, or Unified Memory Architecture, so does NOT treat it as NUMA when scheduling. On top of that, MS changed the scheduler performance to keep it on the same CCX as much as possible before spawning to another CCX, thereby trying to keep latency in the lowest CPU core to core comm latency at all times.

If you understand what was done, you should not fear the new gen at all, instead you should really welcome it. AMD will be discussing this more at the AMD server event on Aug. 7th, followed by Hot Chips the week after where they are headlining.

Now, if your workload needs the mem bandwidth, it may be time to step up to the Epyc Rome platform anyways.

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post #4255 of 4271 (permalink) Old 08-07-2019, 08:01 AM
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Quote: Originally Posted by ajc9988 View Post
Further, your statement is predicated under the argument that the problem was memory bandwidth to the cores and NOT the latency causing stale data.
Actually, my concern was memory latency not memory bandwidth.




Quote: Originally Posted by ajc9988 View Post
Finally, if you are going off of people saying their isn't enough bandwidth to run 32 cores on 4 channels of memory, that is FALSE.
Nope I was going off the results from tech reviewers...apparently Wendell from Level1Techs investigated the thread scheduling problem.



Quote: Originally Posted by ajc9988 View Post
If you understand what was done, you should not fear the new gen at all, instead you should really welcome it.
I was hoping for memory latency improvements from the 3 gen but it looks like is has gotten a little worst than the 1st gen.



Quote: Originally Posted by ajc9988 View Post
Now, if your workload needs the mem bandwidth, it may be time to step up to the Epyc Rome platform anyways.
No, my work load doesn't need extra bandwidth. It needs move memory capacity. I don't need lower latency either but I just don't want higher latency from future generations. I don't want to step up to the Epyc platform because of the lower CPU frequencies.
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post #4256 of 4271 (permalink) Old 08-07-2019, 11:03 AM
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I've seen screenshots of Threadripper systems running 256GB using the double height 32GB modules. Now that Samsung is producing 256GB modules you shouldn't have a problem with building a TR system which can recognize 2TB of memory.

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post #4257 of 4271 (permalink) Old 08-11-2019, 07:47 AM
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Quote: Originally Posted by adam3234 View Post
Actually, my concern was memory latency not memory bandwidth.





Nope I was going off the results from tech reviewers...apparently Wendell from Level1Techs investigated the thread scheduling problem.




I was hoping for memory latency improvements from the 3 gen but it looks like is has gotten a little worst than the 1st gen.



No, my work load doesn't need extra bandwidth. It needs move memory capacity. I don't need lower latency either but I just don't want higher latency from future generations. I don't want to step up to the Epyc platform because of the lower CPU frequencies.
If you are complaining about "more latency," then you have no CLUE what the new architecture and dies bring.

So, first, every time you leave the CCX, you now have to go through the I/O die. This is to try to standardize the latency for every time it goes off CCX, even to the other CCX on the same die. This simplifies scheduling and helps with stale data.

Now, let me explain what is going on a bit more. AMD has, by default, the memory controllers set to Unified Memory Architecture, with the system seeing all controllers as 1. But, there is the ability, at least for Epyc, to break that UMA into four NUMA nodes, with them seeing each controller as its own node (with the two closest chiplets being part of one node).

There is still variable latencies for each of the four controllers. But with them all centralized, and since doing a memory call, regardless which CCX is doing the memory call, requires the same latency to go to the I/O die for each CCX, then the latency variance, depending on which memory controller must be accessed, is reduced to 25ns for travel on the I/O die at the most, and 6ns at the least. This greatly reduces the overall latency to do a memory call for the farthest latencies seen on the WX processors, while increasing the smallest latencies on the WX processors. What that means is, under my theory of stale data being a huge part of the problem on TR 2970WX and 2990WX, that the memory calls will be, for the most part, standardized moving forward.

Now, because of the added latency for the smallest memory latencies, they doubled the L3 cache. That actually slowed down L3 cache calls. But, it also reduced the number of memory calls. Because it reduced the number of memory calls, it overall enhances the performance of the CPU, which is efficiency through inefficiency.

Here are pics and links to the sources on what you need to know for the changes made for the memory. And please stop thinking that increasing the lowest mem latency is a problem. It is called efficiency through inefficiency. It greatly reduced the highest latency while increasing a little on the lowest latency, while having all latency fairly standardized which helps prevent stale data.

https://www.servethehome.com/amd-epy...-a-knockout/4/

https://www.anandtech.com/show/14694...epyc-2nd-gen/2

https://www.anandtech.com/show/14694...epyc-2nd-gen/7

https://www.servethehome.com/amd-epy...-a-knockout/6/

https://www.anandtech.com/show/14694...epyc-2nd-gen/8
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post #4258 of 4271 (permalink) Old 08-13-2019, 11:06 PM
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Late to the party/site. This build has been through many changes over the last couple years.

Started off with a noctua cooler on it..stepped up to enermax #1...it died after 6 months...then replaced for free with enermax #2...again it died after about 5 or 6 months with the same issue of the pump clogging up the fins with biological growth and corrosion because enermax uses soiled dishwater for coolant and mixed metals in their system. You can rebuild them but it wasn't worth the hassle for me. after #2 died I went custom loop and never looked back. Though because the system was already built and I just didn't care about it being a clean build anymore: it's a bit messy lol. Video card was also added to this loop after the loop was originally done because I originally had a RTX 2080 TI in there, but that card got transferred to my new gaming rig, and my old GTX 1080 got upgraded with a waterblock and put back into the threadripper rig as the threadripper was retired from gaming.

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post #4259 of 4271 (permalink) Old 08-13-2019, 11:32 PM
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Had also played with the above rig a bit for giggles after I had custom loop cooled it just to see how far I could push it for gaming performance. It wasn't prime95 stable at this point but it was stable enough for some shorter tests that didn't hold it at 100% indefinitely. heat was just too much to contain at that point without refrigeration for long test (prime95) stability.

But I managed to pull off 4.3GHz with SMT disabled and 4+0 die settings. memory interleaving set to channel. Managed to catch up to a 7700k for single thread performance! Killed it in multi-thread performance 8 threads vs 8 threads. Not bad for a first gen ryzen on ambient temp cooling!

I highly recommend against trying to push one this far though without a serious custom loop or exotic cooling.
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post #4260 of 4271 (permalink) Old 08-14-2019, 07:39 AM
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Another TR owner late to the party. Here are the particulars:

Threadripper 1950x @4050
MSI MEG X399 Creation (MS-7B92) BIOS 7B92v13
Corsair Vengeance LPX 128GB 2666 C16 @2667 14-16-16-34
eVGA RTX 2070 XC Black Gaming
eVGA Hybrid Kit GPU Water Cooling
Samsung SSD 970 PRO 512GB NVMe x2
Samsung SSD 970 EVO Plus 1TB NVMe x2
Samsung SSD 970 EVO Plus 500GB NVMe x1
Corsair H150i Platinum Pro 360 CPU Water Cooling
Corsair AX1200i Platinum Certified
Corsair ML120 Pro RGB x9 (3x Radiator exhaust, 6x case intake)
CableMod C-Series PRO ModMesh Cable Kit For AX PSU
Lian Li Bauhaus-O11 Dynamic Case (DER8AUER Design)
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Everything is funny as long as it is happening to somebody else.
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