For 2 CCD SKUs, 2 DPC SR configuration seems to be the way to go.
Both the 3600 and 3700X did 1800MHz UCLK on 1 DPC DR config, but most likely due to the discrepancy of the two CCDs in 3900X, it barely does 1733MHz on those DIMMs.
Meanwhile with 2 DPC SR config there is no issue in reaching 1866MHz FCLK/UCLK. That's pretty unfortunate since 8GB DIMMs cannot be considered as desireable or future proof as 16GB ones, due to the 32GB limitation.
Sure 16Gb ICs exist nowdays (hence allowing 16GB SR modules), but none of them can come even close to B-die in terms of frequency and timings.
Phy at AGESA defaults, except ProcODT of 40.0Ohm, which is an ASUS auto-rule for Optimem III.
tRDRDSCL & tWRWRSCL cannot be set < 4 CLK when the UCLK is operating at the limit, but that doesn't seem to affect the latency too much.
4 CLK already provides 100% efficiency for intra BankGroup accesses, but obviously it would ideally be set to 2 CLKs. Same goes for disabling GearDownMode, which seems to de-stabilize UCLK when it is operating close to the limit.
Increasing cLDO_VDDP seems beneficial > 3600MHz MEMCLKs, as increasing it seems to improve the margins and hence help with potential training issues. On previous gen. products it was only useful for shifting the MEMCLK holes, which were
present on certain CPU, motherboard and DIMM combinations. But then again, we never did this kind of MEMCLKs on those parts.
And before you ask. No.
Matisse version of RTC will never be public, sorry