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post #31 of 624 (permalink) Old 07-08-2019, 11:14 AM - Thread Starter
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Regarding the die topology latencies on Matisse, here's what I measured on 3900X at stock.

Spoiler!


The intra-CCX (within the same CCX) latency is static, at roughly < 32ns, while the inter-CCX (CCX to CCX) latency and inter-CCD (CCD to CCD) latencies depend on the fabric frequency (FCLK).
Which makes sense, since the CCXs on the same CCDs are connected together through the fabric, as are the different CCDs (through IO-die).
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post #32 of 624 (permalink) Old 07-08-2019, 11:42 AM
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Are you seeing the same IF frequency cap at 1800MHz as pointed by some other reviews? Could this be a firmware limitation?

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post #33 of 624 (permalink) Old 07-08-2019, 01:02 PM - Thread Starter
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Quote: Originally Posted by thigobr View Post
Are you seeing the same IF frequency cap at 1800MHz as pointed by some other reviews? Could this be a firmware limitation?
1800MHz+ should be doable on all CPU specimens.
I've done 1866 and IIRC 1900MHz as well without any issues.

However, the maximum achievable FCLK depends on the memory configuration as well.
1 DPC SR B-die (i.e. single sided sticks) will be hitting the peaks, and 1 DPC DR B-die will reach 1800MHz and not much higher.
According to some sources with 2 DPC DR sticks you are looking at 1600MHz max. FCLK (haven't tested myself).

Also, 2 CCD parts (3900X and 3950X) should be more picky about FCLK, due to the always present discrepancy in the CCD signaling.
Typically one CCD will prefer lower voltage than the other and so on.
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post #34 of 624 (permalink) Old 07-08-2019, 01:11 PM
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Which voltage would potentially aid in stabilizing high FCLK frequency?
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post #35 of 624 (permalink) Old 07-08-2019, 01:15 PM
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for @The Stilt creating this article and testsing!
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post #36 of 624 (permalink) Old 07-08-2019, 01:22 PM - Thread Starter
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Quote: Originally Posted by larrydavid View Post
Which voltage would potentially aid in stabilizing high FCLK frequency?
Matisse introduced a new voltage adjusment, called cLDO_VDDG. VDDG is the fabric voltage.
At default it is 0.950V however, some motherboards might increase above the default level even at stock settings.

cLDO means the voltage uses a drop-out (LDO = low drop-out) regulator.
Most cLDO voltages are regulated from the two main power rails of the CPU. In case of cLDO_VDDG and cLDO_VDDP, they are regulated from the VDDCR_SoC plane.
Because of this, there are couple rules. For example, if you set the VDDG to 1.100V, while your actual SoC voltage under load is 1.05V the VDDG will stay roughly at 1.01V max.
Likewise if you have VDDG set to 1.100V and start increasing the SoC voltage, your VDDG will raise as well. I don't have the exact figure, but you can assume that the minimum drop-out voltage (Vin-Vout) is around 40mV.
Meaning you ACTUAL SoC voltage has to be at least by this much higher, than the requested VDDG for it to take effect as it is requested.

Adjusting the SoC voltage alone, unlike on previous gen. parts doesn't do much if anything at all.
The default value is fixed 1.100V and AMD recommends keeping it at that level. Increasing the VDDG helps with the fabric overclocking in certain scenarios, but not always.
1800MHz FCLK should be doable at the default 0.9500V value and for pushing the limits it might be beneficial to increase it to =< 1.05V (1.100 - 1.125V SoC, depending on the load-line).
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post #37 of 624 (permalink) Old 07-08-2019, 01:57 PM - Thread Starter
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OP has been update, read unless you already have.
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post #38 of 624 (permalink) Old 07-08-2019, 02:09 PM
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Quote: Originally Posted by The Stilt View Post
1800MHz+ should be doable on all CPU specimens.
I've done 1866 and IIRC 1900MHz as well without any issues.

However, the maximum achievable FCLK depends on the memory configuration as well.
1 DPC SR B-die (i.e. single sided sticks) will be hitting the peaks, and 1 DPC DR B-die will reach 1800MHz and not much higher.
According to some sources with 2 DPC DR sticks you are looking at 1600MHz max. FCLK (haven't tested myself).

Also, 2 CCD parts (3900X and 3950X) should be more picky about FCLK, due to the always present discrepancy in the CCD signaling.
Typically one CCD will prefer lower voltage than the other and so on.
Thanks for confirming this.

"By default: memory, fabric, and memory controller are tied at 1:1:1 ratio. This is true up to DDR4-3600 (1800MHz for all). When you go to 3601+, the IF snaps to 1800MHz, and then DRAM:IMC go 2:1 ratio at whatever mclk you have. You can also go back to 1:1 if you want to try it" - Robert Hallock
https://twitter.com/Thracks/status/1148308354852425729

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post #39 of 624 (permalink) Old 07-08-2019, 02:46 PM
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So B-DIE 16GB DR ram will have trouble going over 1600mhz aka pc3200? Or did I read your previous post wrong?

I'm hoping to get 3600 @ 16-16-16-16 out of my 2x16GB 14's b-die kit
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post #40 of 624 (permalink) Old 07-08-2019, 02:49 PM
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Quote: Originally Posted by gupsterg View Post
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Nice find/share (+rep).

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