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Understanding the sizing and limits of PPT TDC and EDC

 
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post #1 of 6 (permalink) Old 08-24-2019, 07:27 AM - Thread Starter
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Understanding the sizing and limits of PPT TDC and EDC

I have a x570 gigabyte Master and a 3900x.
How cand I find goot values for PPT TDC and EDC?ç
In auto ryzen master sets them in 142/95/140 if I run a benchmark the 3 of them become at 98%-100% use in ryzen master. So is this limiting the OC capabilities? it is dangerous to increase it? how can I find a good value?


This is the theory

Package Power Tracking (“PPT”): The PPT threshold is the allowed socket power consumption permitted across the voltage rails supplying the socket. Applications with high thread counts, and/or “heavy” threads, can encounter PPT limits that can be alleviated with a raised PPT limit.

Default for Socket AM4 is at least 142W on motherboards rated for 105W TDP processors.
Default for Socket AM4 is at least 88W on motherboards rated for 65W TDP processors.

Thermal Design Current (“TDC”): The maximum current (amps) that can be delivered by a specific motherboard’s voltage regulator configuration in thermally-constrained scenarios.

Default for socket AM4 is at least 95A on motherboards rated for 105W TDP processors.
Default for socket AM4 is at least 60A on motherboards rated for 65W TDP processors.

Electrical Design Current (“EDC”): The maximum current (amps) that can be delivered by a specific motherboard’s voltage regulator configuration in a peak (“spike”) condition for a short period of time.

Default for socket AM4 is 140A on motherboards rated for 105W TDP processors.
Default for socket AM4 is 90A on motherboards rated for 65W TDP processors.
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post #2 of 6 (permalink) Old 08-24-2019, 02:39 PM
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Try these values:

PPT: 134
TDC: 87
EDC: 117

Run OCCT CPU stress and if you hit 100 percent on EDC in Ryzen master. Up the EDC value in increments of 1 until you hit 98-99 never 100.

To test the other 2 run cb15/20 all core. watch it in real-time with hwinfo at 500ms.

Adjust TDC/PPT based on your all core clocks with runs of cb 15/20

Last edited by Dazog; 08-24-2019 at 02:57 PM.
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post #3 of 6 (permalink) Old 08-25-2019, 05:15 PM
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Are there any papers or docs about PPT TDC and EDC anyone could link?

Thanks

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post #4 of 6 (permalink) Old 08-27-2019, 09:02 AM
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I have a question related to these parameters. Will it maximize the OC capability of I set them to the maximum values? Sure I understand there are still other factors such as silicon lottery, power supply, cooler, etc... But what would be the answer if only consider the particular single factor?
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post #5 of 6 (permalink) Old 08-28-2019, 09:18 AM
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You can safely maximise any or all of these.

Even when they are maxed out, there are other limiters still present (FIT), which prevent the chip from using voltages that are unsafe to the silicon.

You can use TDC and EDC to limit the frequencies in 256-bit workloads (AVX, AVX2, FMA) if you see the need to do so.
Scalar workloads generally are not as much current limited.

This applies to stock (or PBO) behavior, not to manual OC.
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post #6 of 6 (permalink) Old 08-29-2019, 03:39 PM
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The hysteria is out of control, are your temps out of control causing shutdowns?
If so, what are your Constant VCORE/temps?
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