Few suggestions regarding the controls allowed by the new (AGESA 18.104.22.168) bioses:
- In case you run into a MEMCLK hole, adjust the CLDO_VDDP voltage. The VDDP adjustment window is rather narrow, usually < 100mV. Also the window is neither static or linear. Because of that the setting which is optimal for frequency x might not be optimal for frequency y. Also since the window is not linear, but more of a wave form e.g. VDDP at 975mV might work perfectly fine whereas 980mV won't be able to train the memory. The MEMCLK hole is both CPU and DRAM specific, but so far I haven't seen any evidence it being motherboard specimen specific. This means that swapping either the CPU or the memory (to another CPU or modules) might either introduce or the get rid of the MEMCLK hole. Personally I have 100% success rate in clearing the MEMCLK hole with CLDO_VDDP adjustment (1x R7 1700, 1x R7 1800X and 2x R7 1700X). All of the MEMCLK holes on these CPUs have been cleared using 937 - 1000mV setting. Do note that when you change the CLDO_VDDP voltage, saving the bios settings will not put the new CLDO_VDDP voltage into effect, since the CLDOs can only be programmed during a cold reset or a cold boot. Because of that I suggest that you save the new CLDO_VDDP value and press the reset button before the system has booted up again. Also CLDO_VDDP must be at least 100mV lower than the DRAM voltage at all times. Regardless it is not recommended to exceed 1050mV.
- For Samsung B-die dual rank modules I suggest that 96Ohm ProcODT is used.