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post #16111 of 40644 (permalink) Old 05-20-2017, 05:34 AM
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@Elmor

That worked
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post #16112 of 40644 (permalink) Old 05-20-2017, 05:34 AM
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Seems to me that the new BIOS adds memory speed options, but still has the same issues. After playing around with it, I'm getting F9 boot loops again at 3200 speeds.
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post #16113 of 40644 (permalink) Old 05-20-2017, 05:34 AM
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Originally Posted by MagiRaven View Post

Thank you. I downloaded it and it says I have this part: H5AN8G8N?FR-TFC

I'm guessing that is Hynix AFR?

Kinda depends on what's under that question mark I guess tongue.gif. For my ram It's H5AN8G8NMFR-TFC (so MFR), and in my case bios 9945 seemed to work best (although I'm still testing).
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post #16114 of 40644 (permalink) Old 05-20-2017, 05:37 AM
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Quote:
Originally Posted by elmor View Post

These BIOSes should work fine with your DRAM settings when booting from a fully powered off state.
Command Rate sets how many clock edges to wait after setting up addressing (how long to wait before reading or writing data), while Geardown is lowering the frequency of the commands sent to the DRAM (data speed is still the same).
Can you try changing AI Overclock Tuner to Default? Did you flash the 0003 BIOS?

Software reading or DMM? Software readings are flaky.
It should fix problems like this, yes.
Command Rate and Geardown are adjustable now. The difference now is different AMD firmware which are better for specific cases.
You're only seeing 16GB of memory, I think you need to do some debugging and check which DRAM sticks and slots are working.

Booting from a fully powered off state should be fixed in the new versions and not cause DRAM training to fail. Some software needs updating to be able to read the added ratios.
You can try changing the CLDO_VDDP setting (in AMD CBS, don't remember exactly which submenu), it's the replacement for VDDP found under Tweaker's paradise. Our setting is not affecting anything anymore, AMD changed the internal LDO setting. It can help stabalize things and even help with the memory frequency hole. Recommended values are around 900-1000mV, default is 950mV.
See the above recommendation, also try different values for ProcODT. Far from all systems can run 3600 MHz, it depends on the CPU/MB/DRAM.
We've tested it internally to 3200 MHz.
That would be the memory frequency hole, you can also try CLDO_VDDP as above. But why do 3200 when you can get 3466.
Try setting tRDRD_sc = 1. Is only AIDA affected or do you see a performance drop in any real world application?
3200 MHz can still be tricky on some systems which has worse margin (CPU and MB). 3066 probably works at least?

No 3066 for this memory, but CPU-Z is telling me my memory is 1T, even though I set 2T. Checking again to make sure the settings did not revert to Auto in the BIOS.
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post #16115 of 40644 (permalink) Old 05-20-2017, 05:39 AM
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This works ok but Windows sees 2033Mhz.



Are these SPD readings ok?


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post #16116 of 40644 (permalink) Old 05-20-2017, 05:41 AM
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Few suggestions regarding the controls allowed by the new (AGESA 1.0.0.6) bioses:

- In case you run into a MEMCLK hole, adjust the CLDO_VDDP voltage. The VDDP adjustment window is rather narrow, usually < 100mV. Also the window is neither static or linear. Because of that the setting which is optimal for frequency x might not be optimal for frequency y. Also since the window is not linear, but more of a wave form e.g. VDDP at 975mV might work perfectly fine whereas 980mV won't be able to train the memory. The MEMCLK hole is both CPU and DRAM specific, but so far I haven't seen any evidence it being motherboard specimen specific. This means that swapping either the CPU or the memory (to another CPU or modules) might either introduce or the get rid of the MEMCLK hole. Personally I have 100% success rate in clearing the MEMCLK hole with CLDO_VDDP adjustment (1x R7 1700, 1x R7 1800X and 2x R7 1700X). All of the MEMCLK holes on these CPUs have been cleared using 937 - 1000mV setting. Do note that when you change the CLDO_VDDP voltage, saving the bios settings will not put the new CLDO_VDDP voltage into effect, since the CLDOs can only be programmed during a cold reset or a cold boot. Because of that I suggest that you save the new CLDO_VDDP value and press the reset button before the system has booted up again. Also CLDO_VDDP must be at least 100mV lower than the DRAM voltage at all times. Regardless it is not recommended to exceed 1050mV.

- For Samsung B-die dual rank modules I suggest that 96Ohm ProcODT is used.
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post #16117 of 40644 (permalink) Old 05-20-2017, 05:48 AM
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With the new BIOS my AUTO BCLK is 100.6?

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post #16118 of 40644 (permalink) Old 05-20-2017, 05:49 AM
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My results: wheee.gif
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post #16119 of 40644 (permalink) Old 05-20-2017, 05:53 AM
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Quote:
Originally Posted by jugs View Post

With the new BIOS my AUTO BCLK is 100.6?

Has been for ages now.
Set 100.0 manually.
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post #16120 of 40644 (permalink) Old 05-20-2017, 05:54 AM
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Quote:
Originally Posted by The Stilt View Post

- For Samsung B-die dual rank modules I suggest that 96Ohm ProcODT is used.

Any other hints for using 2x16 GB Dual Ranked Samsung B dies with 1.0.0.6? I can boot just fine with 80 or 96 ProcODT, with up to 3200/100 @ 14-14-14-34 timings at least, but no matter what I do, including for example 18-18-18-38 timings, and fiddling with the RTTs, I always run into a random bit errors after some time. Could the CLDO_VDDP also help with that?

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