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post #20661 of 40878 (permalink) Old 06-22-2017, 10:08 AM
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There is a bug in 1401: When you navigate back from Advanced Page > AMD CBS > UMC Common Options > DDR Memory Mapping you land at AMD CBS, not at UMC Common Options. This can get confusing.

Closing in to 500% HCI on 1401, using P-state CPU OC at 3.9 GHz:

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post #20662 of 40878 (permalink) Old 06-22-2017, 10:26 AM
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Too slow.

If one meditiates on that long enough, one may achieve wry-Zen enlightenment.

Rig running Ryzen [email protected] GHz, [email protected] MT/s, Linux Mint 18.1 on Asus C6H
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post #20663 of 40878 (permalink) Old 06-22-2017, 10:30 AM
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Quote:
Originally Posted by Timur Born View Post

There is a bug in 1401: When you navigate back from Advanced Page > AMD CBS > UMC Common Options > DDR Memory Mapping you land at AMD CBS, not at UMC Common Options. This can get confusing.

Closing in to 500% HCI on 1401, using P-state CPU OC at 3.9 GHz:
Warning: Spoiler! (Click to show)

Nice smile.gif .

I struggled with ~3400/3466MHz at C14 1T on 1401 for stability. 3200MHz/3333MHz seems max on that for me at C14 1T. Trying now on 9943 as that was the one I had ~3500MHz stable in both CPUs but C16 2T redface.gif .

Yeah noted that bug, been busy with getting my HCI memtest platinum tester t-shirt to report tongue.gif .
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post #20664 of 40878 (permalink) Old 06-22-2017, 10:36 AM
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I'm pretty happy with my settings, i just finish 1 hour GSAT error free, (i'll launch a longer test this night) even with my tight timming.

Testing 64 Gb is a just a big hassle. (if anyone know a fast method ?)


I'll add my bios setting later ^^ setting.txt 19k .txt file

Attached Files
File Type: txt setting.txt (19.1 KB, 102 views)

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post #20665 of 40878 (permalink) Old 06-22-2017, 11:04 AM
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Is your tRDRDSC at 1 CLK and xSCL values at 2 CLK?
If not, it is useless frown.gif

How important is the xSCL values being at 2? I am running 3466 with primary timings at 14-14-14-14-34-1T w/ 32gb. However, it seems unstable with xSCL being at 2 without raising voltages dramatically.

For instance would running at 3200 with primary timings of 14-14-14-14-34-1T be faster if xSCL is at 2?
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post #20666 of 40878 (permalink) Old 06-22-2017, 11:04 AM
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Few more timing sets.

HQ B-die - 3200MHz "Safe" 1.350V



UHQ B-die - 3200MHz "Fast" 1.350V



HQ B-die - 3333MHz "Safe" 1.350V



UHQ B-die - 3333MHz "Fast" 1.350V



HQ = e.g. 3000C14, 3200C15, 3600C16, 3600C17 rated B-die kits
UHQ = e.g. 3200C14, 3600C15 rated B-die kits

These timings are stable on my 3600C15 kit with < 1.350V voltage (1.340V bios setting).
In 3200MHz "Fast" example, tCL 13 would be otherwise doable (this kit is rated 13.333 CLK tCL-tRCD-tRP timings at 3200MHz) however AGESA issue affecting tCWL prevents using it at the moment.

For the best real world performance disable both BankGroupSwap and BankGroupSwapAlternative options, when using 1 DPC SR modules.
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post #20667 of 40878 (permalink) Old 06-22-2017, 11:11 AM
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A fail in one window hci with this setup, maybe i need help to find the problem. After 3 hci fails i find a setup that can run 200 percent, first 20, second 45. Im near the stability i guess, but i need to see what is failing. This tests are so long for 32gb, 1000 % is needed anyway or with 500 is enough?

Other question about voltages, HWinfo reinstaled, regcleaned ,tried 2 versions, look the voltages shown on all cores page. They never move, restarted and shutdown but never refresh.





If you see any rare tell me. Cpu is on stock and senseiskew disabled, cad values are auto and Procdt in 96. All the rest that is not shwon here is on auto.

f4.3200c14d 32gb
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post #20668 of 40878 (permalink) Old 06-22-2017, 11:20 AM
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Originally Posted by ItsMB View Post

A fail in one window hci with this setup, maybe i need help to find the problem. After 3 hci fails i find a setup that can run 200 percent, first 20, second 45. Im near the stability i guess, but i need to see what is failing. This tests are so long for 32gb, 1000 % is needed anyway or with 500 is enough?

Other question about voltages, HWinfo reinstaled, regcleaned ,tried 2 versions, look the voltages shown on all cores page. They never move, restarted and shutdown but never refresh.





If you see any rare tell me. Cpu is on stock and senseiskew disabled, cad values are auto and Procdt in 96. All the rest that is not shwon here is on auto.

f4.3200c14d 32gb

Will the errors disappear if you set tRDRDSC to 5 (from 1) and tRDRDSCL & tWRWRSCL to 6 (from 2)?
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post #20669 of 40878 (permalink) Old 06-22-2017, 11:20 AM
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Originally Posted by The Stilt View Post

Few more timing sets.

HQ B-die - 3200MHz "Safe" 1.350V



UHQ B-die - 3200MHz "Fast" 1.350V



HQ B-die - 3333MHz "Safe" 1.350V



UHQ B-die - 3333MHz "Fast" 1.350V



HQ = e.g. 3000C14, 3200C15, 3600C16, 3600C17 rated B-die kits
UHQ = e.g. 3200C14, 3600C15 rated B-die kits

These timings are stable on my 3600C15 kit with < 1.350V voltage (1.340V bios setting).
In 3200MHz "Fast" example, tCL 13 would be otherwise doable (this kit is rated 13.333 CLK tCL-tRCD-tRP timings at 3200MHz) however AGESA issue affecting tCWL prevents using it at the moment.

For the best real world performance disable both BankGroupSwap and BankGroupSwapAlternative options, when using 1 DPC SR modules.

My cl19 4266 modules will run 12-12-12-26 with some tightened subs, have not tried on 3600 cl15 yet, but I did get them running 3466 gear disabled smile.gif
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post #20670 of 40878 (permalink) Old 06-22-2017, 11:25 AM
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