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post #21451 of 40901 (permalink) Old 06-29-2017, 07:06 AM
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Quote:
Originally Posted by kaseki View Post

I think this message can prove helpful to new overclockers here. However, I need to point out a couple of related things. When The Stilt referred to the real-time-termination loadings as {disabled, disabled, RZQ/5} I don't think he meant that the first two parameters were zero ohms. More likely 'disabled' sets them at infinity ohms.

To high a terminating resistance does not increase circuit "stress." It may degrade signal to reflected signal ratio, just as too low a terminating resistance may also degrade signal to reflected signal ratio. This is also true of procODT.

What specifically did you find in the B-die specs about RTT values? I looked and failed to find anything, perhaps from data saturation ennui.

Thanks

This is a message in general, xd. I know that Proct is a termination resistance an does not have any effect on the current, but im showing my results llooking at voltages and temperatures cause i dont know the values that and specific procdt value can influde after a train, i know is just for noise etc.. like on any comunication bus, industrial, or any ethernet etc... More or less that i try to say is that i dont have enough information about all this stuff.

The Rtt values maybe are that infinite i dont know what he mean, maybe a disabled is infinite. I mean that 48 is more close to 0 than 240, its only a conclusion that can be wrong, xD

The B-die document about im talking is the Spec samsung support file on samsung site about our chips, but they only talk about speed to 2666 max, so 3200 is not specified in any caculation. I might be provided by Gskill to amd, and from amd to asus i guess, this is why im talking about the responsability of the vendors of suplly the proper specs. Excuse my confusing words im not a perfect english speaker, and imagine the expressions, xDDDD

I found that I had another different Samsung document than I referred to earlier. An extract of the state table for RTT is below. One can see that with The Stilt's recommendation {nom disabled, wr disabled, park RZQ/5} that RZQ/5 is always used. RZQ/5 is 48 ohms per this document. This value might be expected to reasonably match likely trace impedances, although what the relevant C6H trace impedances are is unknown to me.

Conversely, more or less, the Ramad/Jackalito/HarrySun values of {nom RZQ/3, wr RZQ/3, park RZQ/1} when applied to the state table yield a termination resistance that fluctuates. I'm not sure what advantage that would have.

I'm not certain what your recommendation of {auto, auto, auto} actually does, so I'll just add that to my test matrix. Edit: Discovering an earlier message I missed, I think this is The Stilt's {disabled, disabled, 48 ohm} condition.

For reference, I am presently running RZQ/2 on 1403 for all three parameters from a month-ago recommendation by BoMbY. He didn't answer my question about his rationale for these values. My present thinking is that these impedances may be too high for good matching.

And then there is The Stilt's spasm version of 1403 still to test. Sigh.



from DDR4 SDRAM Specification, Device Operation & Timing Diagram, 2014, page 178

The circuit diagram (simpified, I'm sure) extracted below suggests why there may be a change in DRAM power usage. The lower the terminating resistor, the more current flows to the signal lead and thence to eventually to ground. There are a lot of terminating resistors.


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post #21452 of 40901 (permalink) Old 06-29-2017, 07:14 AM
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Alright, thnx but where can i download realbench 2.54? Can't find it anywhere..
http://dlcdnmkt.asus.com/rog/RealBench_v2.54.zip?_ga=2.118948489.1200526813.1498487937-446180562.1468895089

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post #21453 of 40901 (permalink) Old 06-29-2017, 07:33 AM
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Swapped in the R7 1700 CPU, which has the MEMCLK hole located in the 3212.8 - 3347.2MHz region on dual rank modules and at default CLDO_VDDP voltage. I've usually used 96Ohm ProcODT on B-die dual rank modules, since it seems to provide the best cold booting ability. However it seems that with certain CPU, motherboard and DRAM configurations (even within the same exact spec) 96Ohm ProcODT might be too high and cause signaling issues (extremely random and < 80 in size errors in HCI Memtest). There seems to be some correlation with the memory timings as well, especially with the tWR value.

In some cases it might be that the system will require greater than 80Ohm ProcODT in order to be able to cold boot properly, but the next available option (96Ohm) is too high to maintain the signal integrity. In these cases I would suggest that you move the DIMMs for the normal A2 & B2 slot pair to A1 & B1 slots, since the slots closer to the CPU seem to be able to handle lower ProcODT (80Ohms) than the slots further away from the CPU.

- A2 & B2 slots populated
- ProcODT 80Ohms
- VDDCR_SoC 1.05000V
- DRAM Voltage & Boot Voltage 1.39000V (1.404V actual, keep the runtime and boot options synced)
- CAD Controls "Auto" (0-0/32, 0-0/32, 0-0/32, 24/24/24/24Ohm)
- Rtt_Nom = Disabled, Rtt_Wr = Disabled, Rtt_Park = RZQ/5 (48Ohm) - i.e. "Auto"
- CLDO_VDDP = 975mV (to push the MEMCLK hole further away from the current operating frequency, somewhat enhances cold boot capability)

These settings are pretty fast for a rather low quality B-die DR modules:]

Any reason to disable BGS Alternative instead of BGS?


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post #21454 of 40901 (permalink) Old 06-29-2017, 07:35 AM
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Let us know if you believe there is a real/proven benefit to 0312. I am still at 0310. Is AMD the one that is blocking the EC updates now?
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post #21455 of 40901 (permalink) Old 06-29-2017, 08:01 AM
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EC FW update does not occur via flashback, only the UEFI file as a whole is loaded. The UEFI file contains EC FW as stated by The Stilt.

EC FW update occurs once motherboard has finished posting.

EC FW updating is automatic feature but disabled from UEFI 0902 onwards, except two UEFIs, one publicly available, one not. Timur Born has highlighted both, as I did yesterday.

So as stated by The Stilt 0312 is part of newer UEFIs but I was not gaining it as updating blocked.

So I flash the UEFI that doesn't have block, mobo post, update EC FW, then I can flash any UEFI and it will still be there.

As highlighted some things I do believe have changed for me. Currently testing gaining 3466MHz tight. First I did several setups as previous testing as on EC FW 0310. All of these failed but with less errors from compares I did. I have only 1 error in 1 instance of 16 HCI windows to quash, which is eluding me now.

It maybe a placebo effect of having EC FW 0312 vs 0310, I will have to go over past data more thoroughly.



Could be that it was freaking 16c in my living room... Two weeks ago we ware tweeking with 26c in same room.....
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post #21456 of 40901 (permalink) Old 06-29-2017, 08:01 AM
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Can everyone with > 3200 mhz memory/tight timings post their Performance Test Memory scores please?
It's a free download and nice program, but would like to see how my scores compare to others while tweaking memory. Ryzen seems to get a bad score compared to Intel, and I am sure it is due to the low latency score, yet it gives me 55 for latency, so obviously it is not 55 ns, just some random scoring.

http://www.passmark.com/products/pt.htm

Here you go, best i could do so far @3466, CL15...


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post #21457 of 40901 (permalink) Old 06-29-2017, 08:02 AM
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Originally Posted by kaseki View Post

I found that I had another different Samsung document than I referred to earlier. An extract of the state table for RTT is below. One can see that with The Stilt's recommendation {nom disabled, wr disabled, park RZQ/5} that RZQ/5 is always used. RZQ/5 is 48 ohms per this document. This value might be expected to reasonably match likely trace impedances, although what the relevant C6H trace impedances are is unknown to me.

Conversely, more or less, the Ramad/Jackalito/HarrySun values of {nom RZQ/3, wr RZQ/3, park RZQ/1} when applied to the state table yield a termination resistance that fluctuates. I'm not sure what advantage that would have.

I'm not certain what your recommendation of {auto, auto, auto} actually does, so I'll just add that to my test matrix. Edit: Discovering an earlier message I missed, I think this is The Stilt's {disabled, disabled, 48 ohm} condition.

For reference, I am presently running RZQ/2 on 1403 for all three parameters from a month-ago recommendation by BoMbY. He didn't answer my question about his rationale for these values. My present thinking is that these impedances may be too high for good matching.

And then there is The Stilt's spasm version of 1403 still to test. Sigh.



from DDR4 SDRAM Specification, Device Operation & Timing Diagram, 2014, page 178

The circuit diagram (simpified, I'm sure) extracted below suggests why there may be a change in DRAM power usage. The lower the terminating resistor, the more current flows to the signal lead and thence to eventually to ground. There are a lot of terminating resistors.


I dont know what my recomendation does, xD, i enter on this thread only to make my ram faster to play games properly, xD Since i make a couple of questions and some of you made me to read all the thread, so, i tried to configurate my ram as the best way i could do it. I find some information about these chips too, but never find out that schemes and rtt options that youre showing to me, i just setup the ram by trying 10 diferent setups through 3 bios, and my setup is based on my rare conclusions and on all of your problems along the thread that helped me a lot. I tried to share with you all at many posts. I dont know if my setup is good, but it works on my system, anyway is posible to be wrong, as i said is nothing special. Ty for the info.
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post #21458 of 40901 (permalink) Old 06-29-2017, 08:05 AM
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Any reason to disable BGS Alternative instead of BGS?

The default configuration is BankGroupSwap = Enabled, BankGroupSwapAlternative = Disabled.
These two options are mutually exclusive, meaning they can both be disabled but they cannot be enabled simultaneously.

Disabling BankGroupSwap will improve the real world performance (by couple percent), however the reported bandwidth (e.g. AIDA) decreases by < 6%. Enabling BankGroupSwapAlternative has nearly the same positive effect on the real world performance, while the reported bandwidth remains at the same level with BankGroupSwap = Enabled.

Neither of the BankGroupSwap options should be touched, unless 1 DPC SR modules are used.
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post #21459 of 40901 (permalink) Old 06-29-2017, 08:07 AM
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@gupsterg

Let us know if you believe there is a real/proven benefit to 0312. I am still at 0310. Is AMD the one that is blocking the EC updates now?

Will do smile.gif. No Asus, as this "functionality" was causing board bricking wink.gif .
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Could be that it was freaking 16c in my living room... Two weeks ago we ware tweeking with 26c in same room.....

You're in freezer! tongue.gif I'm at ~25°C today. Weekish ago ~32°C redface.gif .
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post #21460 of 40901 (permalink) Old 06-29-2017, 08:17 AM
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@gupsterg should see me running to work today in rain... Even underpants soaked Lovely British summer is finally here 15c outside raining 2 day constant now biggrin.gif
Thats why i removed A/C unit from my Integra just extra weight to push around biggrin.gif
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