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post #6011 of 40638 (permalink) Old 03-31-2017, 02:22 PM
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This reminds me of a question that has been hanging in my attention background: Why does progressively higher leakage (1700 --> 1800X) correlate with progressively higher maximum clock frequency?

Because these chips have already been pushed so far at stock, that we're already hitting the voltage limits (rather than the usual thermal or clock limits). Silicon with higher SIDD generally requires less voltage at ISO frequency and has at least somewhat better voltage scaling. They draw more current and run hotter than the silicon with lower leakage, but in case the silicon isn't thermally limited that's not a disadvantage but an advantage.

There is a reason why they are binned this way at the factory as well wink.gif Same was done with Vishera 9k-series CPUs. Using high leakage silicon is most likely the only way to produce 1800X models with their 4.1GHz MSCXFC, without breaching the reliability thresholds for VDDCR_CPU.
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post #6012 of 40638 (permalink) Old 03-31-2017, 02:22 PM
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what is your kit?

HyperX Fury CL15 2400MHz. ( kit number is HX424C15FBK4/64 )
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post #6013 of 40638 (permalink) Old 03-31-2017, 02:32 PM
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HyperX Fury CL15 2400MHz. ( kit number is HX424C15FBK4/64 )
2933 whit 4 x 16 module of 2400 memory ? lol , i i realy do not understand anymore, whit this cpu it's all like trowing a dice, like in D&D!!
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post #6014 of 40638 (permalink) Old 03-31-2017, 02:42 PM
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DREAMS OF GETTING A 4k STABLE OC




SHATTERED!!!


@ProTekkFZS

With the Pstate adjusting Vid are you still using some offset as well ?
In the end i would love to be able to set a 50% clock state coz it seems you need very little to take it from underclock to Pstate0
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post #6015 of 40638 (permalink) Old 03-31-2017, 02:57 PM
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No CPU OC.
No BLCK adjustment.
Just going for RAM CLK.

Now on 3200MHz, gonna keep testing and then lower timings and OC CPU.





+rep post-flame-small.gif The Stilt post-flame-small.gif , thank you for your shares thumb.gif .
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post #6016 of 40638 (permalink) Old 03-31-2017, 03:00 PM
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Originally Posted by The Stilt View Post

Because these chips have already been pushed so far at stock, that we're already hitting the voltage limits (rather than the usual thermal or clock limits). Silicon with higher SIDD generally requires less voltage at ISO frequency and has at least somewhat better voltage scaling. They draw more current and run hotter than the silicon with lower leakage, but in case the silicon isn't thermally limited that's not a disadvantage but an advantage.

There is a reason why they are binned this way at the factory as well wink.gif Same was done with Vishera 9k-series CPUs. Using high leakage silicon is most likely the only way to produce 1800X models with their 4.1GHz MSCXFC, without breaching the reliability thresholds for VDDCR_CPU.

Thank you for the clarification. +rep, I think, but I didn't see any change.

Rig running Ryzen [email protected] GHz, [email protected] MT/s, Linux Mint 18.1 on Asus C6H
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post #6017 of 40638 (permalink) Old 03-31-2017, 03:00 PM
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Darn. I was hoping today would a new bios day.

As an off-topic point though, this case looks awesome: (No sound, no air, no liquid, no pump, no dust) But it's 75lbs.



https://www.kickstarter.com/projects/1489140137/nsg-s0-worlds-first-fanless-chassis-for-high-perfo
It's nice but too rich for my blood.
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post #6018 of 40638 (permalink) Old 03-31-2017, 03:03 PM
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((1.425 / 2) / 1000) * Idd

If the current drawn by the domain (Idd) is 100A, then the overshoot will be 71.25mV (81.25 - 91.25mV including the existing 10-20mV overshoot). "Level 2" translates to -50% (i.e. / 2).
Thanks for the answer. Where does that 1.425 in your calculation come from? Did you assume 1.425v Vcore setting instead of my 1.35v example?

And while I have your attention: wink.gif

Why does my 1800X throttle down to x35.3/35.8/36 on different cores during *non* AVX ITB/Linpack loads. Thermal and current don't seem to be the issue, especially since it stays at x37 for hours using AXV, Prime95 or Realbench under higher current.
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post #6019 of 40638 (permalink) Old 03-31-2017, 03:07 PM
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Thank you for the clarification. +rep, I think, but I didn't see any change.

Change in what?
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post #6020 of 40638 (permalink) Old 03-31-2017, 03:09 PM
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Originally Posted by Timur Born View Post

Thanks for the answer. Where does that 1.425 in your calculation come from? Did you assume 1.425v Vcore setting instead of my 1.35v example?

And while I have your attention: wink.gif

Why does my 1800X throttle down to x35.3/35.8/36 on different cores during *non* AVX ITB/Linpack loads. Thermal and current don't seem to be the issue, especially since it stays at x37 for hours using AXV, Prime95 or Realbench under higher current.

No, 1.425 is the default Rll in mOhms.
Load-line affects the Rll (virtually) and Rll and the Idd together define the change in the voltage.

Most likely you are hitting the TDC limit. That's the most common reason why Ryzen throttles below the MACXFRC.
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