Originally Posted by polkfan
Ah i never once used RM to change anything but PBO settings sometimes i always just use it to check the settings as it seems to always report the correct settings.
I was at least impressed that 3800/1900FCLK even booted with auto settings for sure a accomplishment on Asrock haha. I do believe i seen 30Ω.
Quite a lot has been improved to say the least and to be honest even the latency on memory seems improved on crappier setups and good setups so that's a great thing for all.
I kind of wish i had a 2000/1000 CPU to play around with and see if any improvements made it to them. EDC bug is still their and indeed with the FIT bug i can get 100mhz or so more MT speed but to be brutally honest ST turbo works almost as good as the FIT bug.
Have to be honest i wasn't expecting anything new for the Ryzen 3000 parts i really wasn't with Zen 3 coming so i'm guessing its to get ready for Zen 3 and like always the previous Zen family's get to see improvements too.
Yea 1st gen was fun, usually i would say - a finetuned 2700X performs exceptionally well
While we had this limits up
Now what most of it is gone, and the difference between coupled and decoupled mode is only 12ns inter-CCX
We should be able to move up and up without having much penalty
I was expecting AMD to play their hidden card if Intel would launch something dangerous , as there where 30GB/s InterCore bandwith lost for nothing
Which relates to a huge bump in IPC
I struggled a lot to get 4-5GB/s out of the 1700X, only worked if everything was running perfectly
But alone that lead 50-60cb in R15 and some nice boost after lowering L3 Latency with performance Boost and Performance Bias settings
(applying the same inter-core latency fixes that 2nd gen was shipping with)
It was fun, wish i could play a bit more with it - it had a bit of headroom left
CL12 3467MT/s would've been fun, the 14-12-14-12 where stable, but still a bit offsync according to SiSandra
Well, whatever - i had a lot of fun with it
You where forced to keep signal integrity clean, else you could forget anything over 3200MT/s
At least since 2nd gen , stuff didn't change that much , rules still apply
I strongly think, that we should be able to to reach that 2000FLCK wall after all artificial limits are gone
Question would be, how clean does it need to be
Down from 34.4 to 28ohm is already a big step in the right direction
Let's play a bit with voltages
950mV VDDG, 900 VDDP does work well for 8x3733MT/s dual-quad channel according to Yuri
According to IMC design, it should feel very well under 1.05v vSOC
Yes, let's continue to play on that part - we already are making wondeful progress
Hitting 1950 stable FCLK is the next step now
Actually you do pass Y-Cruncher first 3 tests with 1:1 1900 ?
LinX is still too unreliable, but at least Y-Cruncher is consistent so far