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post #621 of 760 (permalink) Old 03-13-2019, 05:23 AM
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Quote: Originally Posted by dalathegreat View Post
Anyone planning to get a 3XXX Threadripper CPU when they launch with this board?
+1
Let's see how much power 7nm 32 cores draws.
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post #622 of 760 (permalink) Old 03-13-2019, 09:46 AM
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yeah, I can barely keep the VRM on this board to 84C or lower at 4.2GHz on my 1950X (1.375V) with liquid cooling. Because of that, I may want to upgrade the board for the VRM, but also for PCIe 4.0. Although, if they allow OCing on the Epyc systems, waiting for 2020 with potentially DDR5 on server systems may make me consider a 1P Asrock rack board. But that is if AMD does the 1P Epyc CPUs at the $500 delta they currently are at and hoping the server boards beef up the VRM on them as well.

But, we will see. And at least it won't be like Intel's TDP lie which pulls WAY more watts than marked. Here's hoping the 32 core power draw is really good.

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post #623 of 760 (permalink) Old 03-13-2019, 11:43 AM
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Quote: Originally Posted by ajc9988 View Post
yeah, I can barely keep the VRM on this board to 84C or lower at 4.2GHz on my 1950X (1.375V) with liquid cooling. Because of that, I may want to upgrade the board for the VRM, but also for PCIe 4.0. Although, if they allow OCing on the Epyc systems, waiting for 2020 with potentially DDR5 on server systems may make me consider a 1P Asrock rack board. But that is if AMD does the 1P Epyc CPUs at the $500 delta they currently are at and hoping the server boards beef up the VRM on them as well.

But, we will see. And at least it won't be like Intel's TDP lie which pulls WAY more watts than marked. Here's hoping the 32 core power draw is really good.
I wouldn't discard PCIe 4.0 on this board, its pcb is thicker than others.
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post #624 of 760 (permalink) Old 03-13-2019, 11:52 AM
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Quote: Originally Posted by ajc9988 View Post
yeah, I can barely keep the VRM on this board to 84C or lower at 4.2GHz on my 1950X (1.375V) with liquid cooling.
And thats stable? 4.2ghz 1950X at only 1.375v?

If so, thats the best 1950x ever... But I don't believe it..
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post #625 of 760 (permalink) Old 03-13-2019, 06:38 PM
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Quote: Originally Posted by Dotachin View Post
I wouldn't discard PCIe 4.0 on this board, its pcb is thicker than others.
Due to signal integrity, you need repeater chips to maintain signal integrity beyond a certain distance. Sure, the first slot will support PCIe 4.0. Will all slots? Likely not. Just a reality.

Quote: Originally Posted by ansha View Post
And thats stable? 4.2ghz 1950X at only 1.375v?

If so, thats the best 1950x ever... But I don't believe it..
Well, if passing an hour of realbench, passing Sisoft Sandra, passing the Cosmo Laundromat scene in blender and the blender benchmark test counts as stable, then yes, it is stable. I purchased this binned chip from Silicon Lottery when they first went on sale for $1250. I couldn't reach that speed due to limitations on my cooling capacity until recently (my loop is 3x480mm rads). It can be a little temperamental if ambient heat is too high, but otherwise is fine.
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post #626 of 760 (permalink) Old 03-14-2019, 04:35 AM
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Quote: Originally Posted by ajc9988 View Post
yeah, I can barely keep the VRM on this board to 84C or lower at 4.2GHz on my 1950X (1.375V) with liquid cooling...

AFAIK VRM components are specced to +110*C , so 84*C is incredibly cold!
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post #627 of 760 (permalink) Old 03-14-2019, 05:02 AM
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Quote: Originally Posted by dalathegreat View Post
AFAIK VRM components are specced to +110*C , so 84*C is incredibly cold!
I wouldn't say "incredibly," but 70-80C is definitely safe. But, the temps for the VRM 1&2 sensors sometimes spaz on me, which sucks. Might be a thing with just my board (you can see the error under Max temp in the image above).



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post #628 of 760 (permalink) Old 03-15-2019, 07:08 PM
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I want to see the memory latency die to die or die to I/O chip before I decide on the 3000 series. With the current 2000 series 32 core chips,half the cores can't be used because of the memory access penalties with only two dies having direct access. Any core usage over about 24-36 threads just hammers the compute times on the threads that have the high memory latency through the extra off die excursion. One of my friends sold off his 2990WX because it couldn't handle running the thread count to 60. Most of my other friends with the 2990WX are only running about half loading to keep the cpu compute times consistent.

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post #629 of 760 (permalink) Old 03-15-2019, 08:21 PM
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Quote: Originally Posted by Keith Myers View Post
I want to see the memory latency die to die or die to I/O chip before I decide on the 3000 series. With the current 2000 series 32 core chips,half the cores can't be used because of the memory access penalties with only two dies having direct access. Any core usage over about 24-36 threads just hammers the compute times on the threads that have the high memory latency through the extra off die excursion. One of my friends sold off his 2990WX because it couldn't handle running the thread count to 60. Most of my other friends with the 2990WX are only running about half loading to keep the cpu compute times consistent.
You are wrong and are repeating wrong information that since has been disproved.
https://www.bit-tech.net/news/tech/c...performance/1/
https://www.overclock3d.net/news/cpu...me_scenarios/1
https://www.anandtech.com/show/13446...dripper-2990wx

It had NOTHING to do with memory bandwidth after the exact same behavior was exhibited when tested with Windows 10 and an Epyc 7551P CPU that had the full eight channels of memory.

There are multiple issues. First is that the NUMA setup in Windows is so old, it was designed to allow pour over to a second node back when Intel had two CPU nodes on a single die for their Xeons but a single memory controller. It did not allow for use beyond the first numa flow to the second one, when the 2990WX has 4 nodes. That means the NUMA situation and scheduler was in part to blame for the performance regression. This behavior was NOT observed on Linux which accounted for the architecture better.

Next, there is the issue of stale data. Due to not having direct memory access, and the way that latency stacks on Threadripper (see my discussion on that here: https://www.overclock.net/forum/379-...l#post27893200 (worth checking out for the rumors on the Zen 3 anyways, which AMD is giving more information on in 5 days at the Game Developer's conference)), you can get a stale data problem (described in the post or two by me above the linked post, toward the end of that post).

Now, AMD has dealt with this to a degree with the I/O die being centralized, allowing for an UMA treatment for memory calls. Meanwhile, for Epyc, the dies are not directly connected with IF to each other, meaning all is routed through the I/O (Mark Papermaster disclosed this months ago). On the other hand, the Ryzen mainstream CPUs will have the CPU dies linked with IF directly, meaning it doesn't need the two hops to the I/O and to the other die for inter-die comms. The reason for this is the fewer the core dies, the less that the chance of data becoming stale is. Meanwhile, for wiring all core dies to each other on a 64 core chip with 8 core chiplets would be a technical nightmare, along with the varying latency potential depending on multiple factors for then going to each other core die may have made it less efficient than standardizing the latency, allowing for a more efficient algo for processing. Either way, overall latency is reduced, although certain latency was increased due to not having direct to memory access.

CorePrio by Bitsum is not a perfect solution, but it is similar to AMD's own solution.

Edit: Here is PCWorld comparing the 2990WX using CorePrio to the 28-core Intel Xeon.
https://www.pcworld.com/article/3336...pu.html?page=2
(only shown on 7-Zip compression test)

Edit 2: Ian Cuttress article from Jan: https://www.anandtech.com/show/13853...dows-scheduler

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post #630 of 760 (permalink) Old 03-16-2019, 05:32 PM
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No you are wrong. I never once stated the hosts I was referencing were running any version of Windows. You read into my post your own bias. Our team almost exclusively runs Linux. The evidence can not challenged. Cpu task completion times increase exponentially to double or triple the normal expected run time when the host is overloaded by running too many tasks. Testing results can be repeated and verified by simply restricting the cpu task count and matches up with the online magazine reviews that showed a performance hit on the 2990WX at around 36 cores engaged out of the 64. If you keep the concurrent cpu task count below about 36, then for a host running approximately 3.9Ghz, the tasks take around 1 hour to finish. When you increase the concurrent task count to 48, then some tasks take about 2 hours to finish. Go to 60 concurrent tasks and a large majority of tasks take around 3-4 hours to finish and the overall average of task completion times stretches out to around 2 hours. So by running too many concurrent cpu task at one time, your daily production actually decreases overall. There is a sweet spot where average completion time is minimal while producing a maximum daily output for the host.

[Edit] The person who sold off his TR 2990WX achieved his desired goal of high production cpu machine by building a dual Xeon cpu host with 56 threads total and can keep all cpu tasks running for approximately the same compute times. The Xeons don't clock as fast as the TR being the most restrictive factor. But his daily output is better with the dual Xeon host with less total amount of threads than his failed TR experiment.

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Last edited by Keith Myers; 03-16-2019 at 05:46 PM. Reason: Add info about what the person built next after dumping 2990WX
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