Well quite liking the ACB 4.075GHz OC, performance seems good. The other aspects are improved temps, lower voltage used on average and increased MHz for ACB. Minor possible loss on 1T performance (gotta try some SuperPi to see this better).
Moved on to testing 3466MHz The Stilt whilst on 4.075GHz ACB. I have decided to bump VID for OC from tested 1.281V to 1.287V to guard against any issues which my testing of ~5hrs may not have revealed. SOC I was tempted to bump again only +12.5mV from last used but decided I'll go with a +18.75mV. So currently my SOC voltage/RAM MHz attained is looking like this:-
3200MHz with 0.900V set in UEFI, used The Stilt 3200MHz Safe timings, but TRC 44 TRFC 256 (VDIMM: 1.35V).
3333MHz with 0.912V set in UEFI, used The Stilt 3333MHz Fast timings (VDIMM: 1.37V).
3400MHz with 0.925V set in UEFI, used The Stilt 3466MHz timings (VDIMM: 1.37V).
3466MHz with 0.943V set in UEFI, used The Stilt 3466MHz timings (VDIMM: 1.37V).
All of above 1T GDM: Off, starting point of 0.900V was just picked, 3466MHz still under testing.
OMG, I know my C6H, C7H and ZE have been really clean, soldering looked all sound, out of all 3 board only 1 has 1 slightly skewed inductor placement.
I wouldn't spend too much time chasing getting GDM: Off working.
All I can say is I used 5 differing CPUs on C6H and all accepted 1T GDM: Off, all reached 3333MHz and 3 reached 3466MHz, 1 reached ~3500MHz 2T C16. Same RAM kit and another used on TR+ZE has also worked 1T GDM: Off on upto 3466MHz The Stilt. The C7H has had the F4-3200C14D-16GTZ now upto 3466MHz 1T GDM: Off The Stilt setup.
Thank you as always. VCORE and SOC SVI2 looks on the £ to me
, DRAM from SIO chip I adjusted a few days ago in HWINFO and is sound so far.
UEFI is set at VID: 1.287V SOC: 0.943V DRAM: 1.37V, polling rate: 750ms
Code 8 on C7H was instability due to targeted setup, if occurs on a tested OC profile then something was overlooked and instability occurred. It could be various things related to setup, that just made instability occur.