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post #2731 of 4424 (permalink) Old 10-08-2019, 10:47 AM
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Quote: Originally Posted by pelegow View Post
Hi folks,

Its been over a week that I assembled my rig and I can`t

Can't keep it running long enough to post your question? That would really suck.

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post #2732 of 4424 (permalink) Old 10-08-2019, 10:47 AM
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GBT-MatthewH: I can't seem to run dual GPUs in SLI along with a 10GB NIC in the third PCIE slot. I'm also running two NVME SSDs. It appears I don't have enough PCIE lanes to do all of this. How do the PCIE lanes break down on the Master, factoring in that I'm only using NVME storage, no SATA? Spec wise, I should have plenty of lanes for this, as far as I can tell.


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post #2733 of 4424 (permalink) Old 10-08-2019, 10:55 AM
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Quote: Originally Posted by Bart View Post
GBT-MatthewH: I can't seem to run dual GPUs in SLI along with a 10GB NIC in the third PCIE slot. I'm also running two NVME SSDs. It appears I don't have enough PCIE lanes to do all of this. How do the PCIE lanes break down on the Master, factoring in that I'm only using NVME storage, no SATA?
Here is the link to PCIE Block Diagram Documents: https://drive.google.com/file/d/193t...3xZwShiAD/view

When you have 2 GPUs they both run @ X8 leaving the other 4 from the CPU to the 1st NVME slot. Maybe could add the NIC to a PCIE slot that runs through the chipset.
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post #2734 of 4424 (permalink) Old 10-08-2019, 10:59 AM
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Quote: Originally Posted by wmunn View Post
wouldn't a pair of 1080 cards consume the entire x16 pci lanes, meaning that adding another card would cause conflict with not enough PCI lanes available to use? If that is not the case, I would think PCI lane conflict is at the root of this particular issue.
Quote: Originally Posted by panni View Post
Hmm not really. One PCIE4 X16 lane has as much bandwidth as two PCIE3 X16 lanes AFAIK. One might try running both cards in PCIE3 X8 to verify that, though.
Quote: Originally Posted by pschorr1123 View Post
Here is the link to PCIE Block Diagram Documents: https://drive.google.com/file/d/193t...3xZwShiAD/view

When you have 2 GPUs they both run @ X8 leaving the other 4 from the CPU to the 1st NVME slot. Maybe could add the NIC to a PCIE slot that runs through the chipset.
Awesome, thanks man! Those diagrams are just what I was looking for. I was wondering how the wireless stuff factored into the PCIE usage, and those pics are a huge help! +REP!

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post #2735 of 4424 (permalink) Old 10-08-2019, 11:07 AM
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I have strange issue - yesterday I turned off PC and everything was fine. Today I turned it on, and it seems that SYS_FAN4, SYS_FAN6 and SYS_FAN5 (Aorus Pro) doesn't report fan speed, and Fans are spinning like crazy. I wasn't doing any updates yesterday. Whit might be wrong?

EDIT:
I swapped SYS_FAN4 with SYS_FAN2 - fan connected to #2 is OK, and this connected to #4 is not monitored (runs full speed) even if it worked fine in #2 few seconds ago ... might it be a faulty MoBo?

Last edited by _barat_; 10-08-2019 at 12:17 PM.
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post #2736 of 4424 (permalink) Old 10-08-2019, 11:10 AM
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Quote: Originally Posted by Bart View Post
Awesome, thanks man! Those diagrams are just what I was looking for. I was wondering how the wireless stuff factored into the PCIE usage, and those pics are a huge help! +REP!

NP, They are on the 1st page of this thread along with some other documentation GB Matthew posted.

For a block diagram of the X370 platform I had to get that from Level1 Techs back in 2017

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post #2737 of 4424 (permalink) Old 10-08-2019, 12:07 PM
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Quote: Originally Posted by pschorr1123 View Post
NP, They are on the 1st page of this thread along with some other documentation GB Matthew posted.

For a block diagram of the X370 platform I had to get that from Level1 Techs back in 2017
After reading those and tons of others, I'm still baffled as to why this doesn't work. In theory, PCIE lanes aren't an issue since the x8 / x8 is dedicated to GPU, and there are 8 multi-purpose lanes outside of that (4 of which are for NVME). That *should* leave plenty of lanes for the 10GB NIC. Heck, the top Aorus board includes a 10GB embedded NIC (as those pics indicate), and lanes obviously aren't an issue there. I know the Asus NIC works, since I'm testing that on a Crosshair 7 Hero and it works just fine. Even on a riser cable. I wonder if there's something quirky with this NIC and the Aorus Master. Can't see it, since the NIC is Aquantia chipset, just like the embedded one on the top Aorus board, but who knows.

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post #2738 of 4424 (permalink) Old 10-08-2019, 12:19 PM
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Quote: Originally Posted by Bart View Post
After reading those and tons of others, I'm still baffled as to why this doesn't work. In theory, PCIE lanes aren't an issue since the x8 / x8 is dedicated to GPU, and there are 8 multi-purpose lanes outside of that (4 of which are for NVME). That *should* leave plenty of lanes for the 10GB NIC. Heck, the top Aorus board includes a 10GB embedded NIC (as those pics indicate), and lanes obviously aren't an issue there. I know the Asus NIC works, since I'm testing that on a Crosshair 7 Hero and it works just fine. Even on a riser cable. I wonder if there's something quirky with this NIC and the Aorus Master. Can't see it, since the NIC is Aquantia chipset, just like the embedded one on the top Aorus board, but who knows.
You could try removing one of the GPU's just to see if the NIC works then. At least you would know it's not some sort of incompatibility with the MB.
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post #2739 of 4424 (permalink) Old 10-08-2019, 12:31 PM
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Quote: Originally Posted by Dibiase View Post
You could try removing one of the GPU's just to see if the NIC works then. At least you would know it's not some sort of incompatibility with the MB.
I have a custom hard-tubed loop, so that's a painful process. Downsides of water cooling life! When I get some time, I need to tinker with the BIOS more, maybe see if I can disable the 2nd PCIE slot from there. I also haven't tried disabling all the onboard wireless stuff. An official ticket to Gigabyte wouldn't hurt either. I suspect I'm missing something.

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post #2740 of 4424 (permalink) Old 10-08-2019, 01:18 PM
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Quote: Originally Posted by panni View Post
That's perfectly fine, why do you want to change this?
I was thinking that maybe it's responsible for a higher CPU temperature than it shouldn't be.

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