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post #4141 of 4317 (permalink) Old 03-18-2019, 12:19 PM
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Ok i was able to tighten a little the timings. This timing is stable and rock solid with 1.42v. I tested with tm5 with configuration v2 and modified for 20 cycles. tested multiple times. Tested also on game very CPU bound, like BFV and is rock solid. The CPU is solid, with that voltage it is stable with 4.25 but for now i put 4.225 just for testing ram. By The Way is impossibile for me to go further. 3533 or 3600, or up, makes some errors.
I tried :
-PROC ODT 48 to 60
-Tried Tfaw 24.
-Tried the SCL to 4 from 3
-Tried Different Trfc like 333, or 380, nothing.
-Tried also 14-14-14-30-44. And 15-15-15-15-32-48.
-Tried also Gear down Enable, and Tried to set up to 1.48v on Ram Voltage.
-Tried to set different RTT NOM , like disable and RZQ/7. Tried also some RTT PARK From /5 to /3(80).
-And yes.... tried also with CPU at Stock Freq.
All this attempt failed to stabilize anything over 3466.
Any idea about enything else i can try?
Is possible that is the motherboard, Asrock Taichi, limit?
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post #4142 of 4317 (permalink) Old 03-19-2019, 01:42 AM - Thread Starter
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Quote: Originally Posted by Markz View Post
Ok i was able to tighten a little the timings. This timing is stable and rock solid with 1.42v. I tested with tm5 with configuration v2 and modified for 20 cycles. tested multiple times. Tested also on game very CPU bound, like BFV and is rock solid. The CPU is solid, with that voltage it is stable with 4.25 but for now i put 4.225 just for testing ram. By The Way is impossibile for me to go further. 3533 or 3600, or up, makes some errors.
I tried :
-PROC ODT 48 to 60
-Tried Tfaw 24.
-Tried the SCL to 4 from 3
-Tried Different Trfc like 333, or 380, nothing.
-Tried also 14-14-14-30-44. And 15-15-15-15-32-48.
-Tried also Gear down Enable, and Tried to set up to 1.48v on Ram Voltage.
-Tried to set different RTT NOM , like disable and RZQ/7. Tried also some RTT PARK From /5 to /3(80).
-And yes.... tried also with CPU at Stock Freq.
All this attempt failed to stabilize anything over 3466.
Any idea about enything else i can try?
Is possible that is the motherboard, Asrock Taichi, limit?


If you reduce the processor frequency to 4000 MHz, you will get more overclocking of the RAM
But rather the problem is different, the T-topology of the motherboard always has a mediocre overclocking.
Most timings are far from mine recommendation. I don't know what to expect from your option.

Stand#1 Ryzen Threadripper 2990WX (bacth 1817) @3.8-4.3 + Liqtech 240 * MSI MEG CREATION * G.Skill [email protected] * XFX R7 370 OC * Corsair HX750i * Samsung 960 PRO * Benq BL3201PT
Stand#2 Ryzen 2700X (bacth 1805) @4.2-4.35 + NZXT Kraken x62 * MSI M7 AC * G.Skill [email protected]3733CL14 * MSI GTX 1080 Ti GAMING X * Corsair HX750i * Samsung 970 PRO
DRAM Calculator for Ryzen™ 1.4.1 by me + TM 5 0.12 1usmus config v2 (memory test)
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Last edited by 1usmus; 03-19-2019 at 01:46 AM.
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post #4143 of 4317 (permalink) Old 03-19-2019, 02:26 AM
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Quote: Originally Posted by Markz View Post
Ok i was able to tighten a little the timings. This timing is stable and rock solid with 1.42v. I tested with tm5 with configuration v2 and modified for 20 cycles. tested multiple times. Tested also on game very CPU bound, like BFV and is rock solid. The CPU is solid, with that voltage it is stable with 4.25 but for now i put 4.225 just for testing ram. By The Way is impossibile for me to go further. 3533 or 3600, or up, makes some errors.
I tried :
-PROC ODT 48 to 60
-Tried Tfaw 24.
-Tried the SCL to 4 from 3
-Tried Different Trfc like 333, or 380, nothing.
-Tried also 14-14-14-30-44. And 15-15-15-15-32-48.
-Tried also Gear down Enable, and Tried to set up to 1.48v on Ram Voltage.
-Tried to set different RTT NOM , like disable and RZQ/7. Tried also some RTT PARK From /5 to /3(80).
-And yes.... tried also with CPU at Stock Freq.
All this attempt failed to stabilize anything over 3466.
Any idea about enything else i can try?
Is possible that is the motherboard, Asrock Taichi, limit?
You need to first settle which RZQ values are "best" and the same with procODT. You find some stable settings and then push those up and down to see if it's better or worse for stability and note it down until you find the "perfect" combo. (RZQ/7, RZQ/3, RZQ/1) <--- the most "universal" setting I've found stable 99% though there are alternatives to it depending on mobo/ram/cpu combos. It's easy enough to start with.
ProcODT gets more sensitive the higher speed you want to push and tighter timings. SO if it's stable with a large assortment you aren't on the edge enough to judge which is the "best". If you go to low you get no boot or issues to boot. There aren't many values to try in the end but 3-4 in a range and settling on the best in the end. I found motherboard plays a part on which is best. My Gigabyte and Biostar needs this different (43.6 and 53.3 for comparison)

I didn't see if you had gen1 ryzen or gen 2 ryzen but above 3466Mhz on the Gigabyte I had with my gen1 Ryzen 7 1700 I had to start increasing SoC voltage quite significantly to gain better RAM speeds to stabilize/boot. These were not small increases but large and "over the limit" what is considered safe from if you ask anybody else here or elsewhere on the net.
I fully know gen 2 2000 series doesn't need as much but I don't see people try to push voltage higher to eliminate that prospect. It's fine granularity changing. Not every step of voltage behaves the same and might need adjustments elsewhere to stabilize, and some voltage ranges aren't stable at all.
I found it to be a game of perfectly matching frequency with the right voltage and settings. There were several settings that needed to be just right for speeds above 3600Mhz to work at all in length. 3600mhz and below was much easier from my own experience, there is was "easy" to "overkill" to try speeds above to work error free(though to get them to boot was easy enough(just increase SoC voltage)

This Biostar is impossible though in comparison with same cpu/ram. I'm missing all the settings I want to tweak to see if I can get it to work. (3200Mhz is max on it to even boot properly) Though it has better characteristics otherwise but so much more finicky with what it accepts. Boot process is really sensitive to any instabilities and will reset if so to any large degree. Gigabyte just pushed trough the instabilities and let me into Windows and corrupt stuff over and over until I fixed the correct settings to stabilize for stability.

Memory timings are "trivial" as if you don't have them to low for your current speed and voltage it's nothing compared to try set the other settings correct for any combination of timings to work without errors.

NEW: Biostar x480GT8 ~4.0Ghz CPU, 3200Mhz RAM.... not really better
OLD: Ryzen 7 1700 @ ~4.0Ghz, Gigabyte GA-AB350 Gaming 3, F25 BIOS Agesa 1.0.0.6
4x8Gb Kingston HX434C19FB2K2/16 3466C19 1.2V @ 3733Mhz 16.(17).23.17.34.71.tRFC 568 1T 1.490V (Micron E-die 16nm)
Corsair LPX 2x8Gb 2666C16R @ 3200Mhz 14.(17).17.17.31.49...(260) 1T1.470V (Micron B-die 25nm)
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post #4144 of 4317 (permalink) Old 03-19-2019, 02:44 AM - Thread Starter
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Quote: Originally Posted by ajc9988 View Post
Did not realize that was added with Pinnacle Ridge, which is cool. I'm still on a first gen 1950X. But, that addressed the first point.

With UCLK, it still is tied between the MCLK and UCLK, the difference here is the selection of the divisor used. So separate from the sync and async capabilities, the UCLK setting deals specifically with just the divisor.

When Summit Ridge was being worked on, the Stilt mentioned that in MB debug mode, they could change the ratio for MCLK and UCLK so that the uncore, which is the infinity fabric, would run 1:1. In the final product, which carried through to Pinnacle Ridge, the divisor or ratio of MCLK to UCLK was set 2:1. Many found it easier to refer to it as being clocked to what the RAM's single data rate would be, instead of using the double data rate frequency defined by the user. https://forums.anandtech.com/threads.../post-38778725

AMD has already announced that IF, which acts like an uncore, will have double the bandwidth with Zen 2. Aside from other changes that may have occurred to IF, along with the UMC, etc., the easiest way to double bandwidth would be to double the clockspeed. If not adding an independent clock gen for that, and redesigning all of what you mentioned, you could leave them tied together and just change the divisor to what was even capable on first gen Zen in debug mode (obviously, there may have been stability issues with the first gen or two using a 1:1 divisor for the relationship between those components, which is why 2:1 was used in the final products, something that seems resolved with Zen 2). And I'm not saying it was trivial solving the issue, to be clear, rather that it is the most obvious way to approach the issue.

So, as you said, adding in IF between the I/O die housing the UMC and the core chiplets means latency will go up due to having to transverse the IF to get to the UMC. If you are leaving the UMC MCLK and UCLK tied, then changing the divisor would double the speed of the IF, but more importantly lower the latency with the increase in speed. It is like keeping the latency timing the same, but instead of using 1600MHz, you use 3200MHz, so that the real life latency in ns is reduced a fair amount. This is what I believe the setting for UCLK is referring to, the divisor that set IF to half the speed of the memory, which changing that divisor changes the ratio, thereby allowing for the increase in speed, which translates to bandwidth and lower latency.

"XFR Enhancement:
1) FCLK Frequency
2) MEMCLK Frequency
3) UCLK DIV1 MODE:
a) Auto
b) UCLK==MEMCLK
c) UCLK==MEMCLK/2"

For this, I am relying specifically on the selection 3 under XFR enhancements, where (3)(b) would be 1:1 for UCLK to MEMCLK, and where (3)(c) would set it to a 1:2 ratio, which is what was used on Zen 1 and Zen+. This would leave them being tied together intact, instead just changing one factor in the relationship of how they are tied together.

As such, the UCLK would be defining the MEM/IF relationship separate from the sync and async related to core clock and other clocks that would be effected. Does that make more sense why I see the UCLK divisor as separate from your explanation of the sync and async relationship of clocks?

Edit: and this is for the community more than you Yuri-

While looking through a couple other forums, I've seen comments denigrating IF due to its speed being slower than the ringbus on Intel or Mesh on Intel chips. Frequency is NOT what matters, although it points to two factors that do matter: (1) bandwidth, and (2) latency.

Bandwidth is what determines how much data can pass over the connection in a given period of time (where we get Gbps in relation to ethernet, etc.). Each fabric used has a different amount that it is able to transfer, so that speed will effect the bandwidth the fabric carries, but the bandwidth is what is important, not the speed. It doesn't matter what speed is run if the amount of data between the two is equal, which leads to latency then being what helps determine which is faster if the bandwidth is equal.

A good example of this principle is looking at HBM2 vs GDDR. GDDR uses a smaller bus interface, but clocks really fast. HBM2 has a very wide data bus, but runs at much slower speeds. This means that you can get the same amount of bandwidth from each tech, but the frequency each runs on is very different. Because of this, the impact of latency is then considered. Not going to dive in too deep there, but wanted to show that simplistically looking at frequency alone does not necessarily give an idea on how something functions.
Why will not work 1: 1 (UCLK: MEMCLK) on current generations of processors:

1) UCLK is not able to work with adequate voltage at frequencies above 1900-2000 MHz, respectively, we can not overclock the RAM more then 1900-2000mhz, we lose bandwidth and improve data access delays

2) The internal interfaces are designed for specific frequencies and have certain signal / noise tolerances.

3) Separate components of the memory controller (buffers and caches) no overclocking options. They also have design limitations and they are bottlenecks. Confirmation of this high frequency memory, which do not bring use (over 3533)

At the moment, I'm afraid to predict something because the limiting IF frequency in UCLK mode == MEMCLK may limit the overclocking of RAM. Accordingly, we will lose memory bandwidth and delays will worsen. In this case, we will not have enough two memory channels even for a single-chip configuration.

About the new communications interface, the broader one you wrote about. This is true, they say about it :

* CAKE CRC perf bounds Control
* CAKE CRC perf bounds
* ACPI SLIT Distance Control
* ACPI SLIT remote relative distance
* ACPI SLIT virtual distance
* ACPI SLIT same socket distance
* ACPI SLIT remote socket distance
* ACPI SLIT local SLink distance
* ACPI SLIT remote SLink distance
* ACPI SLIT local inter-SLink distance
* ACPI SLIT remote inter-SLink distance

But the width of the interface, as you wrote above at identical frequencies, will not bring an improvement in the delays, because fine tuning timings will remain.
A confirmation of this will also be published on TechpowerUP

Stand#1 Ryzen Threadripper 2990WX (bacth 1817) @3.8-4.3 + Liqtech 240 * MSI MEG CREATION * G.Skill [email protected] * XFX R7 370 OC * Corsair HX750i * Samsung 960 PRO * Benq BL3201PT
Stand#2 Ryzen 2700X (bacth 1805) @4.2-4.35 + NZXT Kraken x62 * MSI M7 AC * G.Skill [email protected]3733CL14 * MSI GTX 1080 Ti GAMING X * Corsair HX750i * Samsung 970 PRO
DRAM Calculator for Ryzen™ 1.4.1 by me + TM 5 0.12 1usmus config v2 (memory test)
How to update BIOS correctly + Unlocked AMD_CBS for Ryzen motherboard

Last edited by 1usmus; 03-19-2019 at 02:54 AM.
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post #4145 of 4317 (permalink) Old 03-19-2019, 06:08 AM
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Quote: Originally Posted by 1usmus View Post

If you reduce the processor frequency to 4000 MHz, you will get more overclocking of the RAM
But rather the problem is different, the T-topology of the motherboard always has a mediocre overclocking.
Most timings are far from mine recommendation. I don't know what to expect from your option.
Quote: Originally Posted by Nighthog View Post
You need to first settle which RZQ values are "best" and the same with procODT. You find some stable settings and then push those up and down to see if it's better or worse for stability and note it down until you find the "perfect" combo. (RZQ/7, RZQ/3, RZQ/1) <--- the most "universal" setting I've found stable 99% though there are alternatives to it depending on mobo/ram/cpu combos. It's easy enough to start with.
ProcODT gets more sensitive the higher speed you want to push and tighter timings. SO if it's stable with a large assortment you aren't on the edge enough to judge which is the "best". If you go to low you get no boot or issues to boot. There aren't many values to try in the end but 3-4 in a range and settling on the best in the end. I found motherboard plays a part on which is best. My Gigabyte and Biostar needs this different (43.6 and 53.3 for comparison)

I didn't see if you had gen1 ryzen or gen 2 ryzen but above 3466Mhz on the Gigabyte I had with my gen1 Ryzen 7 1700 I had to start increasing SoC voltage quite significantly to gain better RAM speeds to stabilize/boot. These were not small increases but large and "over the limit" what is considered safe from if you ask anybody else here or elsewhere on the net.
I fully know gen 2 2000 series doesn't need as much but I don't see people try to push voltage higher to eliminate that prospect. It's fine granularity changing. Not every step of voltage behaves the same and might need adjustments elsewhere to stabilize, and some voltage ranges aren't stable at all.
I found it to be a game of perfectly matching frequency with the right voltage and settings. There were several settings that needed to be just right for speeds above 3600Mhz to work at all in length. 3600mhz and below was much easier from my own experience, there is was "easy" to "overkill" to try speeds above to work error free(though to get them to boot was easy enough(just increase SoC voltage)

This Biostar is impossible though in comparison with same cpu/ram. I'm missing all the settings I want to tweak to see if I can get it to work. (3200Mhz is max on it to even boot properly) Though it has better characteristics otherwise but so much more finicky with what it accepts. Boot process is really sensitive to any instabilities and will reset if so to any large degree. Gigabyte just pushed trough the instabilities and let me into Windows and corrupt stuff over and over until I fixed the correct settings to stabilize for stability.

Memory timings are "trivial" as if you don't have them to low for your current speed and voltage it's nothing compared to try set the other settings correct for any combination of timings to work without errors.
Quote: Originally Posted by 1usmus View Post
Why will not work 1: 1 (UCLK: MEMCLK) on current generations of processors:

1) UCLK is not able to work with adequate voltage at frequencies above 1900-2000 MHz, respectively, we can not overclock the RAM more then 1900-2000mhz, we lose bandwidth and improve data access delays

2) The internal interfaces are designed for specific frequencies and have certain signal / noise tolerances.

3) Separate components of the memory controller (buffers and caches) no overclocking options. They also have design limitations and they are bottlenecks. Confirmation of this high frequency memory, which do not bring use (over 3533)

At the moment, I'm afraid to predict something because the limiting IF frequency in UCLK mode == MEMCLK may limit the overclocking of RAM. Accordingly, we will lose memory bandwidth and delays will worsen. In this case, we will not have enough two memory channels even for a single-chip configuration.

About the new communications interface, the broader one you wrote about. This is true, they say about it :

* CAKE CRC perf bounds Control
* CAKE CRC perf bounds
* ACPI SLIT Distance Control
* ACPI SLIT remote relative distance
* ACPI SLIT virtual distance
* ACPI SLIT same socket distance
* ACPI SLIT remote socket distance
* ACPI SLIT local SLink distance
* ACPI SLIT remote SLink distance
* ACPI SLIT local inter-SLink distance
* ACPI SLIT remote inter-SLink distance

But the width of the interface, as you wrote above at identical frequencies, will not bring an improvement in the delays, because fine tuning timings will remain.
A confirmation of this will also be published on TechpowerUP

That really clears up what I have been finding with Zen. Bandwith and latency between CPU and RAM is really hard to pin point optimal settings.

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post #4146 of 4317 (permalink) Old 03-19-2019, 06:14 AM
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Quote: Originally Posted by 1usmus View Post


If you reduce the processor frequency to 4000 MHz, you will get more overclocking of the RAM
But rather the problem is different, the T-topology of the motherboard always has a mediocre overclocking.
Most timings are far from mine recommendation. I don't know what to expect from your option.
Before to re-test with CPU overclocking, i always test the ram stability, with cpu at stock clock. Only when i passed some tm5, i apply the overclock on CPU. BTW what is very different in this timing from your raccomandation?

For Nighthog in the attachment(Attached Thumbnails) in the post before, i putted in my best combination of timing and impedences

Last edited by Markz; 03-19-2019 at 06:30 AM.
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post #4147 of 4317 (permalink) Old 03-19-2019, 06:43 AM
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After looking at your result in attached image I can't really say too much more than mention the RZQ/RTT values you got working there are much different from what I could run with my setups.(barely bootable or many errors with both RttNom & RttWr disabled.) Completely not optimal for myself. (edit: though disabled/disabled/ RZQ/6 boots but not tested enough)

Did you play around with the DrvStr values at above speeds? I found often you could play with them a little at higher and "edge" settings for some extra stability. But you often needed diffrent DrvStr values for each voltage/other settings. 20/24 usually works most of the time but at times you could get better results with higher values. But I found this mostly apply to the earliest BIOS with older AGESA, new Agesa usually worked with close to stock/AUTO or 20/20/20/20, 24/24/24/24. New BIOS usually didn't need the 60/40Ohm combinations I used at the old AGESA versions.
I can mention 20/20/20/20 usually wasn't optimal. 24/20/24/24 or 20/20/20/24 <-- was kinda what worked best last I tried.
A observation I made was the higher values you used here the more issue you had using higher RAM voltage. I think it was heat related. (60 Ohm values)

There can be had stability with tweaking AddrCmdSetup, CsOdtSetup, CkeSetup. Those were what enabled me going above 3600Mhz and get stable results on my Gigabyte for 3733Mhz stock/auto worked up to 3600Mhz but after they needed tuning.

NEW: Biostar x480GT8 ~4.0Ghz CPU, 3200Mhz RAM.... not really better
OLD: Ryzen 7 1700 @ ~4.0Ghz, Gigabyte GA-AB350 Gaming 3, F25 BIOS Agesa 1.0.0.6
4x8Gb Kingston HX434C19FB2K2/16 3466C19 1.2V @ 3733Mhz 16.(17).23.17.34.71.tRFC 568 1T 1.490V (Micron E-die 16nm)
Corsair LPX 2x8Gb 2666C16R @ 3200Mhz 14.(17).17.17.31.49...(260) 1T1.470V (Micron B-die 25nm)

Last edited by Nighthog; 03-19-2019 at 07:00 AM.
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post #4148 of 4317 (permalink) Old 03-19-2019, 09:06 AM
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Hi!!!

Sorry if this message is not correctly write here. I have problems when DRAM Calculator.

I have this hard:
Case: Raijintek Ophion EVO
MB: Asus ROG Strix X470-I Gaming
CPU: AMD Ryzen 7 2700X
GPU: KFA2 GeForce® RTX 2080 OC
STG: M.2 Samsung 950 PRO 500GB, SSD Samsung 750GB, HDD WD Green 3TB
RAM: Ballistix Tactical Tracer RGB 16GB DDR4-3000 (x2) 32GB
PS: Corsair SF600
Keyboard: Logitech G710+
Mouse: Logitech G502 Proteus Spectrum
Monitor: HP L2045W (Monitor temporal)
OS: W10 Pro
FANs: Corsair ML120PRO (x3)

And I use Thaiphoon Burner to see full spec of my RAM



After I write parameters in DRAM Calculator and do this error:



With this text in details:

See the end of this message for details on invoking
just-in-time (JIT) debugging instead of this dialog box.

************** Exception Text **************
System.FormatException: Input string was not in a correct format.
at System.Number.ParseDouble(String value, NumberStyles options, NumberFormatInfo numfmt)
at Ryzen_DRAM_Calculator_1._1._0.Form1.Current_Delay_ Time()
at Ryzen_DRAM_Calculator_1._1._0.Form1.metroTile4_Cli ck(Object sender, EventArgs e)
at System.Windows.Forms.Control.OnClick(EventArgs e)
at System.Windows.Forms.Button.OnClick(EventArgs e)
at System.Windows.Forms.Button.OnMouseUp(MouseEventAr gs mevent)
at MetroFramework.Controls.MetroTile.OnMouseUp(MouseE ventArgs e)
at System.Windows.Forms.Control.WmMouseUp(Message& m, MouseButtons button, Int32 clicks)
at System.Windows.Forms.Control.WndProc(Message& m)
at System.Windows.Forms.ButtonBase.WndProc(Message& m)
at System.Windows.Forms.Button.WndProc(Message& m)
at System.Windows.Forms.Control.ControlNativeWindow.O nMessage(Message& m)
at System.Windows.Forms.Control.ControlNativeWindow.W ndProc(Message& m)
at System.Windows.Forms.NativeWindow.Callback(IntPtr hWnd, Int32 msg, IntPtr wparam, IntPtr lparam)


************** Loaded Assemblies **************
mscorlib
Assembly Version: 4.0.0.0
Win32 Version: 4.7.3362.0 built by: NET472REL1LAST_C
CodeBase: file:///C:/Windows/Microsoft.NET/Framework/v4.0.30319/mscorlib.dll
----------------------------------------
Ryzen DRAM Calculator 1.1.0
Assembly Version: 1.4.0.0
Win32 Version: 1.4.0.1
CodeBase: file:///G:/Programas/Overclock-Tests%20PC/Configurar%20RAM%20en%20AMD/DRAM-Calculator-for-Ryzen-1.4.1/DRAM%20Calculator%20for%20Ryzen%201.4.1.exe
----------------------------------------
System.Windows.Forms
Assembly Version: 4.0.0.0
Win32 Version: 4.7.3324.0 built by: NET472REL1LAST_C
CodeBase: file:///C:/WINDOWS/Microsoft.Net/assembly/GAC_MSIL/System.Windows.Forms/v4.0_4.0.0.0__b77a5c561934e089/System.Windows.Forms.dll
----------------------------------------
System
Assembly Version: 4.0.0.0
Win32 Version: 4.7.3362.0 built by: NET472REL1LAST_C
CodeBase: file:///C:/WINDOWS/Microsoft.Net/assembly/GAC_MSIL/System/v4.0_4.0.0.0__b77a5c561934e089/System.dll
----------------------------------------
System.Drawing
Assembly Version: 4.0.0.0
Win32 Version: 4.7.3190.0 built by: NET472REL1LAST_C
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post #4149 of 4317 (permalink) Old 03-19-2019, 09:30 AM
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Quote: Originally Posted by 1usmus View Post
Why will not work 1: 1 (UCLK: MEMCLK) on current generations of processors:

1) UCLK is not able to work with adequate voltage at frequencies above 1900-2000 MHz, respectively, we can not overclock the RAM more then 1900-2000mhz, we lose bandwidth and improve data access delays

2) The internal interfaces are designed for specific frequencies and have certain signal / noise tolerances.

3) Separate components of the memory controller (buffers and caches) no overclocking options. They also have design limitations and they are bottlenecks. Confirmation of this high frequency memory, which do not bring use (over 3533)

At the moment, I'm afraid to predict something because the limiting IF frequency in UCLK mode == MEMCLK may limit the overclocking of RAM. Accordingly, we will lose memory bandwidth and delays will worsen. In this case, we will not have enough two memory channels even for a single-chip configuration.

About the new communications interface, the broader one you wrote about. This is true, they say about it :

* CAKE CRC perf bounds Control
* CAKE CRC perf bounds
* ACPI SLIT Distance Control
* ACPI SLIT remote relative distance
* ACPI SLIT virtual distance
* ACPI SLIT same socket distance
* ACPI SLIT remote socket distance
* ACPI SLIT local SLink distance
* ACPI SLIT remote SLink distance
* ACPI SLIT local inter-SLink distance
* ACPI SLIT remote inter-SLink distance

But the width of the interface, as you wrote above at identical frequencies, will not bring an improvement in the delays, because fine tuning timings will remain.
A confirmation of this will also be published on TechpowerUP
Great explanation!

What I am talking about in regards to Valhalla/Zen 2, though, is the changes that have been made. "One interesting detail AMD disclosed with their GPU announcement is that the infinity fabric now supports 100 GB/s (BiDir) per link. If we assume the Infinity Fabric 2 still uses 16 differential pairs as with first-generation IF, it would mean the IF 2 now operates at 25 GT/s, identical to NVLink 2.0 data rate. However, since AMD’s IF is twice as wide, it provides twice the bandwidth per link over Nvidia’s NVLink." https://fuse.wikichip.org/news/1815/...zen-2-details/

This suggests that there are non-trivial improvements to the Infinity Fabric for implementation, where the bandwidth supported doubled. Now, pointed out in this quote is that they assume the same number of differential pairs exist as compared to first generation for part of their calculations.

So, moving forward, I'm using publicly available data for discussing what may come in the future generation, not current generation, chips.

1) There is a voltage/power issue with infinity fabric. I cannot find the source at the moment, but someone did an analysis of power draw of the data fabric relative to package power and estimate core power to show that the data fabric is a large power hog. In addition to voltage and power, that also means that the data fabric will contribute to the heat on the chip and eat into the TDP, depending on how calculated, meaning keeping it cool is another issue that needs considered. In arguendo, that means that if they accomplished doubling the bandwidth by doubling the speed through changing the ratio so that IF2 can run at the same speed of the DDR, rather than using the divisor of 2, there are still questions on how the reduction of power was accomplished and the heat levels generated by the data fabric. This means they may have found a way around the effective cap that you mentioned. But the point on limiting memory overclock is still valid (more on that in a moment).

2) This is true, it is designed for certain frequencies and signal to noise ratios. In fact, in light of discussing point one, I mentioned that IF gen 1 was a power hog, which then translates into heat. Heat can effect the signal to noise ratios in specific scenarios, as thermal radiation can degrade and decay the signal integrity of the data.

3) Great point. And this suggests to implement this with Zen 2, AMD would have had to address those areas in the design and testing phase to allow for a 1:1 setting, where current gen CPUs could not accomplish that, whether it be the cache or timings that were implemented for a 1:2 ratio to optimize that setting or the power requirements or the signal integrity. They may even have it so that when the divisor is changed, it automatically switches to a pre-determined set of timings and settings for the UMC to allow for it to work (like slightly loosening timings due to the speed being higher, which the lower timings would be too aggressive at the higher speed).

As we both have mentioned in this discussion, if AMD were to achieve double the frequency and bandwidth with the IF gen 2, it would not be a trivial undertaking. There are many notable changes that would need made, and would be an impressive evolving of the data fabric.

Even if accomplished, your point is still valid that by using UCLK == MCLK could limit memory frequencies, thereby limiting the ram overclock which loses bandwidth and increases latency. Let's say that the rumor is true that the officially supported memory speed increases to 3200MHz, something rumored awhile ago, but that no new information or speculation on this front has been given for 3-5 months. If the IF2 has been tuned to support in 1:1 mode 3200MHz, then it may not allow too much speed beyond this. That could leave low 3000MHz speeds as necessary to use 1:1 mode, where higher frequencies would not be possible.

Now, AMD, by moving the memory controller to the I/O die, should be able to bin the performance of the memory controller and I/O die overall. That can help to achieve the higher official memory speed. But, that also means that, in certain scenarios, like mainstream chips with dual channel memory support which requires less bandwidth than potentially that of Threadripper or Epyc, it may be more beneficial to use 1:2 mode to allow the memory to hit high 3000 to 4000MHz on the binned I/O dies, as the benefits of using 1:1 may not scale, while also reducing the frequency selected, thereby effecting memory bandwidth and latency. It would also increase the power draw, causing more heat, etc.

On the other hand, for Threadripper and Epyc users, with quad channel and octochannel memory configurations, achieving higher speeds is a bit more difficult, and they have more potential memory bandwidth than the mainstream CPUs. I would argue this is where the true benefit of a 1:1 setting would lie.

This has a couple implications:

A) the new divisor likely is not going to be backwards compatible with current generation offerings from AMD,

B) the new divisor may not be the best setup for mainstream CPUs on the new generation, depending on different factors, and

C) when overclocking with the new processors, if the above changes were made to allow lower power draw and higher frequencies, a person may want to explore the trade offs of using 1:1 vs 1:2 relative to the stable function of memory and IF, in the event that memory overclocking is able to achieve higher frequencies due to binning of I/O dies.

So I must admit, I have numerous embedded assumptions about what would have had to have taken place for this to be achievable on Zen 2. It also shows why the function of data fabric is important, and why Intel and Nvidia are bidding for the purchase of Mellanox for their IP.

Sorry if I missed something. Just waking up with my morning coffee, so forgive if my morning cloudiness effected some element of this discussion. If nothing else, this shows how much we still don't know about the upcoming platform.

And I'm looking forward to seeing that article!

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post #4150 of 4317 (permalink) Old 03-19-2019, 06:38 PM
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Quote: Originally Posted by Markz View Post
Ok i was able to tighten a little the timings. This timing is stable and rock solid with 1.42v. I tested with tm5 with configuration v2 and modified for 20 cycles. tested multiple times. Tested also on game very CPU bound, like BFV and is rock solid. The CPU is solid, with that voltage it is stable with 4.25 but for now i put 4.225 just for testing ram. By The Way is impossibile for me to go further. 3533 or 3600, or up, makes some errors.
I tried :
-PROC ODT 48 to 60
-Tried Tfaw 24.
-Tried the SCL to 4 from 3
-Tried Different Trfc like 333, or 380, nothing.
-Tried also 14-14-14-30-44. And 15-15-15-15-32-48.
-Tried also Gear down Enable, and Tried to set up to 1.48v on Ram Voltage.
-Tried to set different RTT NOM , like disable and RZQ/7. Tried also some RTT PARK From /5 to /3(80).
-And yes.... tried also with CPU at Stock Freq.
All this attempt failed to stabilize anything over 3466.
Any idea about enything else i can try?
Is possible that is the motherboard, Asrock Taichi, limit?
Try that
3533_XFR-disable+0.025offsetLLC5
SOC1.037vLLC5
MEM1.445v
VDDP-auto


Quote: Originally Posted by 1usmus View Post

If you reduce the processor frequency to 4000 MHz, you will get more overclocking of the RAM
But rather the problem is different, the T-topology of the motherboard always has a mediocre overclocking.
Most timings are far from mine recommendation. I don't know what to expect from your option.
@1usmus , have you noticed different memory stable timings when using SATA and M.2 PCI-X SSD? I noticed that my old stable timings with SATA SSD were not stable when change to M.2 SSD, Needing to change some to get 3466mhz stable.

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Last edited by numlock66; 03-19-2019 at 06:43 PM.
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