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NEW!!! DRAM Calculator for Ryzen™ 1.5.1 (overclocking DRAM on AM4) + MEMbench 0.7 (DRAM bench)

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post #4131 of 4607 (permalink) Old 03-17-2019, 02:11 AM - Thread Starter
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It is time to tell you about the features that will appear in Ryzen 3000


Spoiler!


Translation into simple language. We have:

1) New memory controller with partial error correction for nonECC memory
2) Desktop processor with two (2 CCD) chiplets on board, 32 threads maximum
3) New MBIST (Memory built-in self-test)
4) Core watchdog - is a fail/safe function used to reset a system in case the microprocessor gets lost due to address or data errors
5) XFR - at the moment I do not see anything special about it, the algorithm and limits have been updated. Scalar Controll come back with new processors.
6) Updated core control has a symmetric configuration of the active cores . In 2CCD configurations, each chiplet has its own RAM channel in order to minimize latency to memory access. 1 channel on 8 cores will be a bottleneck if you use the system in the default state.

UPD: point number 6 is questionable, perhaps there will be a special long-range interface for connecting a chiplet with IO

This is not all information which I will gladden you in the near future

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post #4132 of 4607 (permalink) Old 03-17-2019, 02:42 AM
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Quote: Originally Posted by 1usmus View Post
It is time to tell you about the features that will appear in Ryzen 3000
I have AGESA 0.0.7.2 on my Biostar Board with my Ryzen 7 1700 and I can access "SMU and PSP Debug Mode", "MBIST" from your list of updates. "Chipselect Interleaving" is available as well.
Though unsure if any of the things actually work though, tried MBIST enabled/disabled but didn't notice any difference really.

Something you didn't mention is the "Trusted Computing Module" I found I could enable, (was default) and it showed a AMD vendor module installed (nothing external mounted so a integrated module in cpu/chipset) now available?

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post #4133 of 4607 (permalink) Old 03-17-2019, 02:55 AM - Thread Starter
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Quote: Originally Posted by Nighthog View Post
I have AGESA 0.0.7.2 on my Biostar Board with my Ryzen 7 1700 and I can access "SMU and PSP Debug Mode", "MBIST" from your list of updates. "Chipselect Interleaving" is available as well.
Though unsure if any of the things actually work though, tried MBIST enabled/disabled but didn't notice any difference really.

Something you didn't mention is the "Trusted Computing Module" I found I could enable, (was default) and it showed a AMD vendor module installed (nothing external mounted so a integrated module in cpu/chipset) now available?
hmm...perhaps they forgot to include a restriction for these functions

I did not find any mention of "Trusted Computing Module"...i can not comment

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post #4134 of 4607 (permalink) Old 03-17-2019, 03:30 AM
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Quote: Originally Posted by 1usmus View Post
hmm...perhaps they forgot to include a restriction for these functions

I did not find any mention of "Trusted Computing Module"...i can not comment
Some screen caps of BIOS features:
Attached Images
File Type: bmp TPM.bmp (3.00 MB, 160 views)
File Type: bmp MBIST.bmp (3.00 MB, 138 views)
File Type: bmp SMUandPSP.bmp (3.00 MB, 118 views)
File Type: bmp MemoryMapping.bmp (3.00 MB, 136 views)
File Type: bmp STIBP.bmp (3.00 MB, 119 views)

NEW: Biostar x480GT8 ~4.0Ghz CPU, 3200Mhz RAM.... not really better
OLD: Ryzen 7 1700 @ ~4.0Ghz, Gigabyte GA-AB350 Gaming 3, F25 BIOS Agesa 1.0.0.6
4x8Gb Kingston HX434C19FB2K2/16 3466C19 1.2V @ 3733Mhz 16.(17).23.17.34.71.tRFC 568 1T 1.490V (Micron E-die 16nm)
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post #4135 of 4607 (permalink) Old 03-17-2019, 06:09 AM
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Quote: Originally Posted by Nighthog View Post
Have you tried to go higher on your sub-timings?

For example:
12 tWR
tRDRDSCL/tWRWRSCL 4/4 or 2/2 (I've found 3/3 5/5 are harder to deal with than the even numbers)
10/12 tRTP
tRFC higher? each kit have a limit on how low (ns) they can go. You have 180ns for now stable? When you go higher speeds try to keep it there by adjusting your tRFC to make it so or just pick a random much higher value there to see if it's the issue.
then the tWRWRSD/tWRWRDD 7/7, tRDRDSD/tRDRDDD 5/5 (this is usually safe settings for 99% of the time, adjust these lower when you have something stable for the speed you want as a last adjustment basically) there is not much performance gains here but they have much to do with stability at times when on the edges of your system can do.

EDIT: I noticed you had "GearDownMode" set to disabled... I think this is main culprit if you can't gain higher speeds. (has a high tax on stability as it performs much better with 1T timings than anything else)
You can try to set it enabled to see if you can gain speed but your latency and performance will drop considerably compared to disabled with same settings. It's just to see if you can get so much more speed from your kit otherwise to compensate. (it's a trade-off deal and A/B testing thing to see which gets you more)
Yes i tried to set 7-7-5-5 instead of 6-6-4-4, but...no positive results. I tried also with geardown enbaled Just to see, but It didin't help, and obviously the performance was worse. I tried also to set an higher Trfc with 0 good results. I can try to set the SCL Valute to 4
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post #4136 of 4607 (permalink) Old 03-17-2019, 11:06 AM
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Quote: Originally Posted by 1usmus View Post
It is time to tell you about the features that will appear in Ryzen 3000


Spoiler!


Translation into simple language. We have:

1) New memory controller with partial error correction for nonECC memory
2) Desktop processor with two (2 CCD) chiplets on board, 32 threads maximum
3) New MBIST (Memory built-in self-test)
4) Core watchdog - is a fail/safe function used to reset a system in case the microprocessor gets lost due to address or data errors
5) XFR - at the moment I do not see anything special about it, the algorithm and limits have been updated. Scalar Controll come back with new processors.
6) Updated core control has a symmetric configuration of the active cores . In 2CCD configurations, each chiplet has its own RAM channel in order to minimize latency to memory access. 1 channel on 8 cores will be a bottleneck if you use the system in the default state.

This is not all information which I will gladden you in the near future
The XFR is actually quite impressive. If I read it right, they added FCLK, which we need to find out what that bus is doing. On Intel Skylake, Anand wrote the following:

The register in question is called the FCLK (or ‘f-clock’), which controls some of the cross-frequency compensation mechanisms between the ring interconnect of the CPU, the System Agent, and the PEG (PCI Express Graphics). Basically this means it is to do with data from the processor to the GPUs. So when data is handed from one end to another, this element of the processor manages the data buffers to allow that cross boundary migration in a lossless way. This is a ratio frequency setting which is tied directly to the base frequency of the processor (the BCLK, typically 100 MHz), and can be set at 4x, 8x or 10x for 400 MHz, 800 MHz or 1000 MHz respectively.
https://www.anandtech.com/show/9607/...-optimizations


They also now allow for the clock set on the Infinity Fabric (UCLK) to select the divisor, which means we are looking at IF being clocked equal to the memory frequency at dual rate instead of single rate (like 3200MHz instead of 1600MHz), potentially. That has a lot of implications on performance if I'm reading that correctly! EXCITED!!!

Edit: Anyone better with limits in calculus, here is some data points from a pro Intel review company, PCPerspective (Ryan Shrout ran it and Shrout Research and regularly attacked AMD, but the latency of going off CCX was shown by them, although their memory timings were crap and I get lower latency than they ever achieved as a combination of core clock, memory speed and timings, etc.).
https://www.pcper.com/reviews/Proces...ging-between-t

Another way would be to test Zen or Zen+ with Sisoft Sandra's test for calculating the latency to see the latency at different memory speeds, then, after that, extrapolate out the expected drop in latency for a speed double the single rate, meaning where the limit is that the curve is approaching as latency is not dropping linearly with the speed increase of the memory controller and therefor the Infinity Fabric. This can show how the bandwidth is double for the upcoming infinity fabric changes due to doubling the speed of the fabric, while the latency improvement would be estimated through this calculation. (math is the reason I dropped from engineering/physics in undergrad; the only way to pass calc II is to have taken calc II (even though calc I can handle this math problem)).

With that information, we can estimate a lot about the upcoming performance increase related to reduced latency, as well as looking at whether there were bandwidth limitations on data related to the IF. Unfortunately, we cannot fully get the picture, but a data point is a data point.

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post #4137 of 4607 (permalink) Old 03-17-2019, 08:12 PM
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Could you clarify what you mean by #6? If I understand you correctly then this means that there is a 2CCD mode which allows you to link one memory channel to one chiplet and the other to the second chiplet, and then another non-2CCD mode which simply acts like normal, with both chiplets having access to both RAM channels, is this what you mean? If so, is their any benefit to this, or why would they implement it?
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post #4138 of 4607 (permalink) Old 03-18-2019, 01:09 AM - Thread Starter
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Quote: Originally Posted by jedidude75 View Post
Could you clarify what you mean by #6? If I understand you correctly then this means that there is a 2CCD mode which allows you to link one memory channel to one chiplet and the other to the second chiplet, and then another non-2CCD mode which simply acts like normal, with both chiplets having access to both RAM channels, is this what you mean? If so, is their any benefit to this, or why would they implement it?
This is inside information, not the fact that it is reliable.'
There are 2 scenarios:

1) Each chiplet will receive 2 Unified Memory Controllers, and in the case when there are 2 chiplets in the system, only one Unified Memory Controller will be active for each chiplet.
2) There is no UMC in the chiplet, communication with IO (two UMCs) will occur via the "long-range" link based on serialization (CAKE-> IFOP). That is, all the blocks and interfaces of the Zen architecture will remain but will have a slightly different lineup.

Quote: Originally Posted by ajc9988 View Post
The XFR is actually quite impressive. If I read it right, they added FCLK, which we need to find out what that bus is doing. On Intel Skylake, Anand wrote the following:

The register in question is called the FCLK (or ‘f-clock’), which controls some of the cross-frequency compensation mechanisms between the ring interconnect of the CPU, the System Agent, and the PEG (PCI Express Graphics). Basically this means it is to do with data from the processor to the GPUs. So when data is handed from one end to another, this element of the processor manages the data buffers to allow that cross boundary migration in a lossless way. This is a ratio frequency setting which is tied directly to the base frequency of the processor (the BCLK, typically 100 MHz), and can be set at 4x, 8x or 10x for 400 MHz, 800 MHz or 1000 MHz respectively.
https://www.anandtech.com/show/9607/...-optimizations


They also now allow for the clock set on the Infinity Fabric (UCLK) to select the divisor, which means we are looking at IF being clocked equal to the memory frequency at dual rate instead of single rate (like 3200MHz instead of 1600MHz), potentially. That has a lot of implications on performance if I'm reading that correctly! EXCITED!!!

Edit: Anyone better with limits in calculus, here is some data points from a pro Intel review company, PCPerspective (Ryan Shrout ran it and Shrout Research and regularly attacked AMD, but the latency of going off CCX was shown by them, although their memory timings were crap and I get lower latency than they ever achieved as a combination of core clock, memory speed and timings, etc.).
https://www.pcper.com/reviews/Proces...ging-between-t

Another way would be to test Zen or Zen+ with Sisoft Sandra's test for calculating the latency to see the latency at different memory speeds, then, after that, extrapolate out the expected drop in latency for a speed double the single rate, meaning where the limit is that the curve is approaching as latency is not dropping linearly with the speed increase of the memory controller and therefor the Infinity Fabric. This can show how the bandwidth is double for the upcoming infinity fabric changes due to doubling the speed of the fabric, while the latency improvement would be estimated through this calculation. (math is the reason I dropped from engineering/physics in undergrad; the only way to pass calc II is to have taken calc II (even though calc I can handle this math problem)).

With that information, we can estimate a lot about the upcoming performance increase related to reduced latency, as well as looking at whether there were bandwidth limitations on data related to the IF. Unfortunately, we cannot fully get the picture, but a data point is a data point.
Pinnacle Ridge CPUs also support multiple reference clock inputs. Motherboards which support the feature will allow "Synchronous" (default) and "Asynchronous" operation. In synchronous-mode the CPU has a single reference clock input, just like Summit Ridge did. In this configuration increasing the BCLK frequency will increase CPU, MEMCLK and PCI-E frequencies.

In asynchronous-mode the CPU cores will have their own reference clock input. MEMCLK, FCLK and PCI-E input will always remain at 100.0MHz, while the CPU input becomes separately adjustable. This allows even finer grain CPU frequency control, than the already extremely low granularity "Fine Grain PStates" (with 25MHz intervals) do.

Despite some wild speculation, the asynchronous clocking capability makes no difference to the memory & data fabric (“IF”) frequency relations. These “two” frequencies are permanently tied together in every currently existing Zen design and changing the current topology would require a major overhaul to the foundations of the die.

If there is no UMC in the chiplet, then the delay will increase. Of course, this negative effect can be reduced by applying a new memory controller and new links.

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DRAM Calculator for Ryzen™ 1.5.1 by me + TM 5 0.12 1usmus config v3 (memory test)
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Last edited by 1usmus; 03-18-2019 at 01:20 AM.
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post #4139 of 4607 (permalink) Old 03-18-2019, 06:54 AM
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Quote: Originally Posted by 1usmus View Post
Pinnacle Ridge CPUs also support multiple reference clock inputs. Motherboards which support the feature will allow "Synchronous" (default) and "Asynchronous" operation. In synchronous-mode the CPU has a single reference clock input, just like Summit Ridge did. In this configuration increasing the BCLK frequency will increase CPU, MEMCLK and PCI-E frequencies.

In asynchronous-mode the CPU cores will have their own reference clock input. MEMCLK, FCLK and PCI-E input will always remain at 100.0MHz, while the CPU input becomes separately adjustable. This allows even finer grain CPU frequency control, than the already extremely low granularity "Fine Grain PStates" (with 25MHz intervals) do.

Despite some wild speculation, the asynchronous clocking capability makes no difference to the memory & data fabric (“IF”) frequency relations. These “two” frequencies are permanently tied together in every currently existing Zen design and changing the current topology would require a major overhaul to the foundations of the die.

If there is no UMC in the chiplet, then the delay will increase. Of course, this negative effect can be reduced by applying a new memory controller and new links.
Did not realize that was added with Pinnacle Ridge, which is cool. I'm still on a first gen 1950X. But, that addressed the first point.

With UCLK, it still is tied between the MCLK and UCLK, the difference here is the selection of the divisor used. So separate from the sync and async capabilities, the UCLK setting deals specifically with just the divisor.

When Summit Ridge was being worked on, the Stilt mentioned that in MB debug mode, they could change the ratio for MCLK and UCLK so that the uncore, which is the infinity fabric, would run 1:1. In the final product, which carried through to Pinnacle Ridge, the divisor or ratio of MCLK to UCLK was set 2:1. Many found it easier to refer to it as being clocked to what the RAM's single data rate would be, instead of using the double data rate frequency defined by the user. https://forums.anandtech.com/threads.../post-38778725

AMD has already announced that IF, which acts like an uncore, will have double the bandwidth with Zen 2. Aside from other changes that may have occurred to IF, along with the UMC, etc., the easiest way to double bandwidth would be to double the clockspeed. If not adding an independent clock gen for that, and redesigning all of what you mentioned, you could leave them tied together and just change the divisor to what was even capable on first gen Zen in debug mode (obviously, there may have been stability issues with the first gen or two using a 1:1 divisor for the relationship between those components, which is why 2:1 was used in the final products, something that seems resolved with Zen 2). And I'm not saying it was trivial solving the issue, to be clear, rather that it is the most obvious way to approach the issue.

So, as you said, adding in IF between the I/O die housing the UMC and the core chiplets means latency will go up due to having to transverse the IF to get to the UMC. If you are leaving the UMC MCLK and UCLK tied, then changing the divisor would double the speed of the IF, but more importantly lower the latency with the increase in speed. It is like keeping the latency timing the same, but instead of using 1600MHz, you use 3200MHz, so that the real life latency in ns is reduced a fair amount. This is what I believe the setting for UCLK is referring to, the divisor that set IF to half the speed of the memory, which changing that divisor changes the ratio, thereby allowing for the increase in speed, which translates to bandwidth and lower latency.

"XFR Enhancement:
1) FCLK Frequency
2) MEMCLK Frequency
3) UCLK DIV1 MODE:
a) Auto
b) UCLK==MEMCLK
c) UCLK==MEMCLK/2"

For this, I am relying specifically on the selection 3 under XFR enhancements, where (3)(b) would be 1:1 for UCLK to MEMCLK, and where (3)(c) would set it to a 1:2 ratio, which is what was used on Zen 1 and Zen+. This would leave them being tied together intact, instead just changing one factor in the relationship of how they are tied together.

As such, the UCLK would be defining the MEM/IF relationship separate from the sync and async related to core clock and other clocks that would be effected. Does that make more sense why I see the UCLK divisor as separate from your explanation of the sync and async relationship of clocks?

Edit: and this is for the community more than you Yuri-

While looking through a couple other forums, I've seen comments denigrating IF due to its speed being slower than the ringbus on Intel or Mesh on Intel chips. Frequency is NOT what matters, although it points to two factors that do matter: (1) bandwidth, and (2) latency.

Bandwidth is what determines how much data can pass over the connection in a given period of time (where we get Gbps in relation to ethernet, etc.). Each fabric used has a different amount that it is able to transfer, so that speed will effect the bandwidth the fabric carries, but the bandwidth is what is important, not the speed. It doesn't matter what speed is run if the amount of data between the two is equal, which leads to latency then being what helps determine which is faster if the bandwidth is equal.

A good example of this principle is looking at HBM2 vs GDDR. GDDR uses a smaller bus interface, but clocks really fast. HBM2 has a very wide data bus, but runs at much slower speeds. This means that you can get the same amount of bandwidth from each tech, but the frequency each runs on is very different. Because of this, the impact of latency is then considered. Not going to dive in too deep there, but wanted to show that simplistically looking at frequency alone does not necessarily give an idea on how something functions.

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Last edited by ajc9988; 03-18-2019 at 07:21 AM.
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post #4140 of 4607 (permalink) Old 03-18-2019, 08:06 AM
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