Originally Posted by CJMitsuki
First off why go to [email protected]
when you had [email protected]
running? Even if you got it running, the performance would have been god awful compared to the 3200 profile you had going. Aside from all of that it looks like something is amiss with your set. Either you have a picky set of ram that wants a certain SoC voltage and dont run on anything else or you have some hardware issues. You need to go back to the profile you had working and test different SoC voltages and 1.38v DRAMv. Starting 1.0875 SoC isnt a bad plave to start. Go up a tick or 2 then run a memory test and take note of how long it takes to find an error. If errors are immediate the keep moving on the voltage, if the errors get worse then reset back to 1.0875 and move in the other direction. Dont be afraid to loweR OR bump DRAM voltage a bit. Memory sets are very picky at times, mine being no exception. My SoC has to be right on or I get errors also. You can also play with ProcODT, CAD_Bus, and RttPark for stability. 53.3 ProcODT is usually what ive found runs best, RttPark can offer more stability going to RZQ4 or 3, Ive found that disabling the others is the best (RttNOM and RttWR), Cad_Bus is usually good at 24ohm at lower frequencies but can be tuned to 30ohm and 40ohm offering more stability, Gear Down Enabled will also boost stability at a small latency penalty, Same goes for 2T, so dont be afraid to use either. Power Down enabled is something I havent tested much but it did seem that it wasnt worth the performance hit for any stability that it may have given so I would just keep it disabled. For Samsung BDIE you are going to want to aim for [email protected]
for starters, and I honestly think you can get there but your ram is just being difficult and wants to be picky. Good rule of thumb for starting timings out for picky ram is set 14-14-14-14 then think of tRas and tRC as buddies. When you change one you need to change the other and ill tell you how, its very simple. tCL+tRAS=tRC. You can bump tRC up a couple if needed but never ever go below that equation. tRAS is usually found between the values 20-40, start at 40 which means according to that equation at cl14 you must have tRC no lower than 54. Make the other values auto if you want to just focus on these timings at first but you can input something like 400 or 450 tRFC and can work it down lower later and maybe tRRDS 7, tRRDL 9, and tFAW will almost always be best at this equation (tRRDL*4) so 9*4 means tFAW will be 36. Later on you can work those 3 values down to 4, 6, 24 or even 4, 4, 16 but I wouldnt worry about that too much until you get the hang of some of the timings. Dont be afraid to run timings on auto so you arent overwhelmed, and when making adjustments never make multiple adjustments at one time. You adjust only one timing or setting and then test or else how will you know which of the changes actually made an impact? You wont. Memory OC takes a ridiculous amount of time and research, dont be afraid to take notes as well. Buy a cheap notebook and write everything down for reference as well as read some articles or watch some YouTube videos about ram timings. With plenty of time and patience you will get it but if for some reason nothing of what I told you helps the ram at all then you may need to look to it being a hardware issue of some sort because if you follow what I have said then you should see a positive change. Sorry for typos and rambling on but I have just finished working 14 hours and Im very worn out. If you need any more information just tag me in the message or quote me or something and I will eventually get back to you when I have time. Good Luck. Oh, before I go...When you are wondering if a certain frequency will be an improvement at a different tCL then just use a simple equation (Frequency/tCL=X) the higher the value for X the more potential performance there is so 3200c16 is 200 where 3400c23 is 147.8 so you see the 3400 setup would be trash. If the X value is pretty close then the higher frequency wins. Just work toward getting 3200 down to tCL 14 and you should be fine.
1) tCL + tRAS = tRC - not true
2) (tRRDL * 4) so 9 * 4 means tFAW will be 36 - not true
3) must have tRC no lower than 54 - not true
absolutely every timing is INDEPENDENT
, I advise everyone to forget about these primitive formulas
For batch reading of a given amount of data, the following operations must be performed:
1) activate the row in the memory bank using the ACTIVATE command;
2) issue a command to read READ data;
3) read data coming to the external data bus of the chip;
4) close the line using the PRECHARGE row recharging command (as an option, this is done automatically if you use the "RD + AP" command in the second step).
The time interval between the first and second operations is the "delay between RAS # and CAS #" (tRCD), between the second and third - "CAS # delay" (tCL). The time interval between the third and fourth operations depends on the length of the transmitted packet. Strictly speaking, in memory bus cycles, it is equal to the length of the transmitted packet (2, 4 or 8) divided by the number of data elements transmitted on the external bus in one clock cycle - 1 for SDR type devices, 2 for DDR devices. Conditionally, we call this value "tBL".
It is important to note that the SDRAM chips allow the third and fourth operations to be performed in a sense "in parallel". To be precise, the PRECHARGE command can be used for a number of measures x before the moment at which the last data element of the requested packet occurs, without fear of the occurrence of a "break" condition of the transmitted packet (the latter occurs if the PRECHARGE command is submitted after commands READ with a time interval, less than x). Without going into details, we note that this time interval is equal to the value of the delay of the signal CAS # minus one (x = tCL - 1).
Finally, the time interval between the fourth operation and the subsequent repetition of the first operation of the cycle is the "recharge time of the line" (tRP).
At the same time, the minimum activity time of the line (from the ACTIVATE command to the PRECHARGE command, tRAS), by its definition, exactly corresponds to the time interval between the start of the first and the beginning of the fourth operation. This implies the first important relationship between memory timings:
tRAS, min = tRCD + tCL + (tBL - (tCL-1)) - 1,
where tRCD is the time of the first operation, tCL is the second, (tBL - (tCL-1)) is the third; finally, the subtraction of the unit is due to the fact that the tRAS period does not include the clock on which the PRECHARGE command is given. Reducing this expression, we get:
tRAS, min = tRCD + tBL.
The rather amazing conclusion resulting from the detailed consideration of the data access scheme contained in SDRAM memory is that the minimum value of tRAS does not depend (!) On the delay value CAS #, tCL. The dependence of the former on the latter is a fairly common misconception, quite often encountered in various manuals on RAM.
The second important relationship between timings follows from the fact that the full cycle of packet data reading - from the 1st stage to its repetition - is called the "minimum time of the line cycle", tRC itself. Since the first three stages, as we showed above, can not take a time shorter than tRAS, and the latter takes a time strictly equal to tRP, we get:
tRC = tRAS + tRP.
Note that some memory controllers allow independent setting of timings tRAS and tRC, which in principle can lead to non-observance of the above equality. Nevertheless, this inequality does not make much sense - it will only mean that the tRAS or tRC parameters will be automatically "adjusted" (in the direction of a larger value) to comply with the equality discussed.
The same goes for the rest of the timings, a vivid example of tFAW = 27 I have for 3666.
p.s. tBL for DDR4 always = 8