NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking DRAM on AM4) + MEMbench 0.8 (DRAM bench) - Page 774 - Overclock.net - An Overclocking Community
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NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking DRAM on AM4) + MEMbench 0.8 (DRAM bench)

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post #7731 of 7823 (permalink) Old 05-22-2020, 03:17 PM
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I guess that makes sense since TR is HEDT......maybe.....

On a different note...does having PageFile set make a difference when it comes to these tests, HCI/Karhu/TM5 ect? Mine is set to whatever Windows sets it to by default.

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post #7732 of 7823 (permalink) Old 05-22-2020, 03:48 PM
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Quote: Originally Posted by Tobiman View Post
New dual rank kit. My CPU won't post above 1800 FCLK even with loose timings. The chip needs almost 1.46volts to reach 4.150ghz. Absolutely garbage chip. I need to get a better R5-3600 but it's a lottery. Or maybe it's my motherboard. Auros B450i. Hopefully, the new B550 boards will be showing up soon.

My chip is about the same, 1.45v and it cant do 4.1 all core, on a CH7 Hero so mine is just as horrible. I will have a 12core baby soon so I will recommission this 3600x to a little server build, going to run it at 3.8ghz


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post #7733 of 7823 (permalink) Old 05-22-2020, 05:15 PM
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Hi guys, not sure if I've missed something. Just tried to "upgrade" from 1.7 to 1.7.3 and noticed the R-XMP button is gone, and also if I try to import a Taiphoon export that works in 1.7, 1.7.3 doesn't populate any values. Am I missing something? Not sure how to use it right now because of this.

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post #7734 of 7823 (permalink) Old 05-22-2020, 05:22 PM
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Nevermind, I was noobing it up and used the wrong export options in Taiphoon. I don't use it much and just had a few things wrong.

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post #7735 of 7823 (permalink) Old 05-22-2020, 05:28 PM
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Quote: Originally Posted by Hequaqua View Post
On a different note...does having PageFile set make a difference when it comes to these tests, HCI/Karhu/TM5 ect? Mine is set to whatever Windows sets it to by default.
The tests do warn when the pagefile is locked, too small or disabled
Difference in testing time yes, in results i am not sure
They request their size, windows just adapts
Quote: Originally Posted by yrelbirb View Post
sad though. as i said, i managed to fixate my micron b die kits at 3400 mhz cl16 with a voltage of 1.45v and it passed 20 cylces of 1usmus even. so... i dont think i can be imc or board limited

will keep trying combos. sadly, due to the quarantine (until wednesday), these kits will stay with me. after that i will send them back via cargo. until then though, gotta keep trying... maybe there's a quirk that i m not aware of that can fix the issue

let's see what veii or 1usmus will tell about this. i hope they do see this problem/message maybe their experience can solve this matter , no idea though

i also would like to add; no overclock on cpu of course. , oh and i even tried disabling core boost XD
(oh and of course, i've tried all kinds of voltages with these hynix kits. 1.4, 1.45v even tried 1.5v.. i tried low voltages too, like 1.30-1.132-1.35 and such.

i tried all of these for 3000 19-19-19-39-58 and it still didn't work.
i also tried upping the tRC to 75 for some reason, yet again, same.
Quote: Originally Posted by 2600ryzen View Post
Maybe swap the ram for a zen2 cpu like the 3300x. That should let you run your micron b die much faster anyway. I couldn't run my current kit above 3133mhz on zen+ now it does up to 3733mhz and I think it's SOC limited and could go higher.
Quote: Originally Posted by yrelbirb View Post
back at my "crappy" micron b-die kits at 3200 mhz cl14...
thank the gods it booted fine.. i got really trippy with the constant amount of boot loops haha

god bless Micron I guess. at least their kits are working appopriately...
The 2700X isn't anywhere near close to it's IMC limits
It only would approach bad signal integrity, if procODT is pushing over 53.3Ω up to set of memory
It has to be rather user error, while i think it's more dust related at this point
3200 has to boot up without issues on 2nd gen
Even with bad predicted settings hitting memory hole, 3200 has to run
The only reason why it wouldn't run is:
- Kit requires too high procODT over 60
- kit requires own set of RTT values, not being able to be predicted
- GDM rounding does trow off IntelXMP profile on it, or board is too stupid to predict correct tRFC and tRDWR values, refusing it to boot
- kit has dust and usage marks on the contacts and need some cleaning
- or kit is just DOA

yrelbirb, can you show a thaiphoon burner report or read out your micron b-dies - corsair version on the sticker
Just for personal comparison sake, i'm curious about them
Your HynixCJR was 18nm or 16nm
I saw they where A2 pcb, soo you will for sure have issues with bad signal integrity and need higher drive impedance
(higher CAD_BUS ClkDrvStrengh ~ first value, near 40-60ohm, if not exceeding 100ohm up to IC)

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post #7736 of 7823 (permalink) Old 05-22-2020, 06:00 PM
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I remember now yes I couldn't get my micron rev D to post properly because of wrong auto TRDWR/TWRRD values like veii says.
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post #7737 of 7823 (permalink) Old 05-22-2020, 06:14 PM
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Quote: Originally Posted by 2600ryzen View Post
I remember now yes I couldn't get my micron rev D to post properly because of wrong auto TRDWR/TWRRD values like veii says.
Back then many people had issues with 1st gen , not being able to post anything over 2933 - because the default cLDO_VDDP was 850mV
850mV covers about 2933-3066MT/s
If it was just 10 more, 860 - it would cover the 3200-3333MT/s region and people would be happy
Same actually for 2nd gen, i think once it defaulted to even 900mV, which is either 2800ish or near 3600~ , nothing in between ^^'
Sadly not many people are aware of this, and a huge thanks goes to 1usmus for figuring out scaling

3266-3333MT/s on first gen was a pain, while it looked just as a logical stepup from 3200
Well, easy was the last thing, this stepup was without modifying cLDO_VDDP not possible
But nah, 3600 can run even with procODT 60Ω on 12nm
For 3733 you'd need 53.3Ω as absolute max, if not even 48Ω for good signal integrity

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post #7738 of 7823 (permalink) Old 05-22-2020, 06:46 PM
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Thanks for the info Veii.

Well just finished the TM5 20 cycles....no issues....woot!

Not bad for a couple pair of mismatched sets of ram. I'm guess the Zen Timings tool reads the first occupied slot on the board since that's where the GSkill was installed. They are in slots 1-3, the Patriot in 2-4.

Maybe it's me, but I'm amazed at these speeds/timings with a SoC of 1.037v and Dram voltage of 1.380v.

Click image for larger version

Name:	32 TM5 20.jpg
Views:	55
Size:	190.3 KB
ID:	348314

I forgot to mention....the Patriot doesn't report temps, but I'm guessing they should probably be within a few degrees of what the GSkill were. Max on Slot 1 42.3°C, Slot 2 44.8°C. I would say that's pretty good......I guess...lol

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post #7739 of 7823 (permalink) Old 05-22-2020, 06:53 PM
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Quote: Originally Posted by Hequaqua View Post
Thanks for the info Veii.

Well just finished the TM5 20 cycles....no issues....woot!

Not bad for a couple pair of mismatched sets of ram. I'm guess the Zen Timings tool reads the first occupied slot on the board since that's where the GSkill was installed. They are in slots 1-3, the Patriot in 2-4.

Maybe it's me, but I'm amazed at these speeds/timings with a SoC of 1.037v and Dram voltage of 1.380v.

Attachment 348314

I forgot to mention....the Patriot doesn't report temps, but I'm guessing they should probably be within a few degrees of what the GSkill were. Max on Slot 1 42.3°C, Slot 2 44.8°C. I would say that's pretty good......I guess...lol
Change your timings up a tiny bit if possible
tRCD WR 14
tRCD RD 18
tRAS 32
tRC 44
tRFC 308-229-141
tWR 14
tCWL 16

you have GDM on, it will round up - and added latency performs far lower than you fixing it by hand
Which kits are you chaining together exactly
Is this board T-Topology ?
Would be interesting to know which memory PCB you chain together - as you might get some significant perf out of it, by putting better kits as the main
While worse ones as slave 1s,3rd slot
I'd also suggest to enable BGS with 4 kits when you want them to work together a bit better

In the future you might also be able to run
tRDWR 9, tWRRD 3 - to give it a bit more bandwidth boost
SCL under 4 i can't imagine sadly here
Rest looks good
Just consider sideeffects of GDM

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Last edited by Veii; 05-22-2020 at 06:55 PM. Reason: calculation mistake, fixed tRAS
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post #7740 of 7823 (permalink) Old 05-22-2020, 07:00 PM
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Quote: Originally Posted by Veii View Post
T-Topology you can imagine spreads the signal as 50% to each set, while Daisy Chain does 75% & 25%
Overall you'd need more VDDG IOD and likely higher procODT impedance and higher RTT Ω for them, overall just stronger drive strengh
Maybe even more ClkDrvStrengh (first CAD_BUS value)
Logically this explains why 4 dimms on daisy chain are a very bad idea, and why T-Topology clocks a bit lower by default on 2 dimm setups

Sadly yes,
as VGGD 1.15ish was used, the only vSOC that can be accepted is 1.2v and higher
Even if you force it lower, as long as VDDG is that high, nothing under +50mV over it will be accepted as vSOC
Inside AMD Overclocking, there is a menu called UNCORE OC , enabling that will disable boards autocorrection on voltage
But i suggest you to hold on these voltage patterns - the 2nd half of the message:
https://www.overclock.net/forum/1805...l#post28424814



The DRAM Calculator can be buggy sometimes on imported calculation
The only way to prove it different is with SiSandra, tho i noticed they are autocorrected in the hidden
tCL is autocorrected directly on boot with GDM on @rastaviper that is readable
But the rest is autocorrected in the hidden - the same goes for tRFC which can be autocorrected in realtime just indicating bad perf if it's too low
Only way to proof it is by a SiSandra report or a long membench delay / maybe even SuperPi 1.5 SX should show a difference
You can adapt tho, tRP often can be lowered with voltage and tRC has wiggle room of -2 under tRAS+tRP in case you want to adjust tRFC better
There is not much of an issue to use only even timings - but it's a reason why i prefer 2T over GDM to use odd timings
They end up just faster, even tho 2T is about as slow to 1T as decoupled mode
The odd timings benefits win at the end
Sadly some bad chips require Half clock GDM mode

B1 is like A1, short trace design - it's a good thing, it can run very tight timings but more sensitive to bad signal integrity
Easier to run tight timings than B2/A2, tho only good till 4000MT/s - later it fails against A2/B2
Both are very sensitive to low end boards, but A1/B1 are easier to run than A2/B2


Want to try something stupid ?
Do you think you could lower tRCD WR a bit ?
i imagine down to 10-12ish, at lowest half of tRCD RD could make sense

Else here is something "stupid"

if tWR 10 is too low, put it back to 12 with tRAS 28
At best you'd then want to push tRP 12, but i am a bit conflicting if current voltage would be enough for tRP 12
If it still fails, just put tRCD WR 10, then you can use tRAS 28 and everything will look fine with this low tRTF of 140ns
^ if you use tRCD WR 10 also put back tWR 12 to match up everything - but idealy this "stupid" try would work with tWR 10
* something aside, would you prefer tRDWR & tWRRD stuff above just aside tRCD and tCL, like tRTP is next to tWR ?
** that would move tRFC set down bellow, of course still with the debug mini tRFC sample/design we all got used to
*** the placeholder is when we unhide another timing inside the bios


Both of these errors are mirror move errors, it's a delay that comes from moving data between different dimms and different banks
Its not MirrorMove128, soo it's likely just 1 value off the correct one
Can be tRP cell pre/re-charge being too slow, tRDWR/WRRD values being off, tRFC being a bit unsync, tWRT_ & tRRD_ values being too tight
Something micro chokes
Can also be tWR making issues
MirrorMove is data cloning between banks - you'll figure it out , just read the mt.cfg to know what error is for what

Happy Testing

Logically red requires orange values unless stated otherwise~

The only thing that looked wrong was tWRRD at 3, should be 4 as you are on 16, not 17 on the tRCDs
or you lower tRCD WR down 2 then tWRRD 3 is fine
cLDO_VDDP over 900mV is only needed when you seak for 1950-2000FCLK or higher than 2000MCLK
900mV here is more than enough for <1900FLCK

Hard question, you want high speed, decouple mode shouldn't bother the 3300X that much at all
4000 ones are A0 PCB - easier to run and you have kinda a low end board, tho if i googled correctly and this is only with 2 slots and hopefully daisy chain layout
A2 PCB would work

4400 are A2 pcb , a custom A1 variance just as A2 for speeds above 4000MT/s
Grab the A2s if this is board is daisy chain, else stay on A0 if this is t-topology, else you'd need to use quite strong impedance to push T-Topology with A2 kits
well both are fine, your goal tho is above 4400MT/s with this ryzen, even above 4600
For low timings couples mode A0 is better as it's easier to run, and maybe you get lucky and get an A1 pcb which is extremely rare on the 4K ones

Kinda +1
You learn the best on the most horrible kits out there xD
HynixMFR to your luck, loves voltage near the 1.55-1.62v
In my signature there are two sets for HynixMFR near 3334MT/s
3400 has such a high stress, only way to hit 3600 is with 3rd gen and stupid voltages (1.62 and above)
3200 is your end goal, 3333 is already pushing the limits - it's MFRs limits
Tho both of my signature are stable but boards do autocorrect as i didn't know at that time the full effects of GDM enabled

You can't drop tCWL under tCL when you have GDM enabled
You could do more if these set of timings run under 2T well enough instead

Green is optimal baseline with GDM enabled
Orange Requires 1.42-1.46v
Red around 1.46-1.48v VDIMM
all depends on PCB Revision (A0,A1,A2)
Black would be dropping SCL to 2 , but that's not possible on low end b-dies
Hi @Veii ,

i have test your suggestion timing 3800mhz @ gdm on. so far so good. anything else i can do to make it tighter? now at 1.4v vdimm & 1.05 vddg. for your info my best stable gdm off is 3600c15 as below.
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Last edited by paih85; 05-22-2020 at 07:05 PM.
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