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post #41 of 279 (permalink) Old 07-09-2019, 04:18 PM
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Hello. is the article here real?

No Asus Motherboards Officially Support the R9 3900x

https://old.reddit.com/r/Amd/comment...upport_the_r9/

AMD Ryzen 7 1800X 3.8 GHZ (NOCTUA NH-U12S SE) ASUS ROG CROSSHAIR VI HERO (Sapphire Nitron+Radeon RX 580 4G) G.SKILL Flare X DDR4-3200Mhz C14 32GB (4x8GB) Samsung 850 PRO 512GB 550MB-520MB/s Sata3 SSD

Last edited by mito1172; 07-09-2019 at 04:23 PM.
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post #42 of 279 (permalink) Old 07-09-2019, 08:04 PM
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Phoronix did a memory scaling article today:
https://www.phoronix.com/scan.php?pa...900x-ram&num=1

► Recommended GPU Projects: [email protected] , [email protected] (FP64) (AMD moreso) ► Other notable GPU projects: [email protected] (Nvidia), GPUGrid (Nvidia) ► Project list


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post #43 of 279 (permalink) Old 07-09-2019, 08:32 PM
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post #44 of 279 (permalink) Old 07-09-2019, 10:59 PM
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Quote: Originally Posted by mito1172 View Post
@elmor

Hello. is the article here real?

No Asus Motherboards Officially Support the R9 3900x

https://old.reddit.com/r/Amd/comment...upport_the_r9/
Shawn Jennings aka Johan45 has this in his review:-

Spoiler!


Source link.

Screenshot link.

Also see some more screenshots here.

I reckon the support pages have not been updated, I do recall at Ryzen 1xxx launch a similar case, you can see similar things in the C6H OCN thread in posts of 2017.
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post #45 of 279 (permalink) Old 07-10-2019, 01:45 AM
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Quote: Originally Posted by elmor View Post
Yes, unless you want higher copy bandwidth.





I suppose theoretically, since each has 16-bit width lanes for writes (32 bits for reads) which makes 2x16=32 bits total. It will depend on the application and if it uses both dies to access memory. From what I remember AIDA64 always tests memory using core 0 which wouldn't show any improvement, but that could have changed. I re-do these tests with 3900X when I get my hands on one.

It would seem that the decoupled FCLK is locked at 1800Mhz while the MCLK is increased with the faster kits not as was originally communicated, running at a 2:1 ratio.That can be seen in gaming frame rates as memory speeds imcrease above 3600MT/s

Please remember that those AMD slides in the presentation Deck are a little misleading and do not show teh full picture.

If we do the Maths
L3 Cache is clocked at CPU frequency yet the slides show that it is communicating at 32 bytes /cycle. At a CPU frequency of 4200MHz, that is approximately 440GB/s of theoretical Bandwidth and is reflected in the Aida Cache benchmarks with real world cache throughput between Core and Cache in the 400+GB/s range depending on CPU frequency. The Timings required for the Cache memory are baked into the UEFI and not user adjustable

The infinity Fabric interconnects are also shown at 32 bytes/cycle yet they are capped at 1800 MHz. with 3600MT/s Ram installed that is a maximum theoretical bandwidth of 56.7GB/s.

On the 3900X slide, it shows that there are 2 interconnects between the CCDs and the I/O die. but what is not shown, is that those 2 inteconnects are merged into a single interconnect, also running at 32 bytes/cycle at 1800Mhz that connects the data fabric in the IO Die to the Memory Controller circuitry. That aspect of Zen is in common with Zen 1 and 1+. That single interconnect to the memory limits Ryzen CPUs to a total 56.7GB/s between CPU Cores and the dual Channel RAM that in itself also has a theoretical Max bandwith that matches the Infinity Fabric up to 1800Mhz.Above that frequency, teh Infinity Fabric will start to bottleneck the Installed 4000+MT/s Ram

That 56.7GB/s of total end to end bandwidth also has to be shared with the GPU and it's DMA memory access requirements. A 2080ti running at full speed is demanding upwards of 15GB/s of data, that, while separated directly from the hardware by the kernel virtual memory management, ultimately has to come from the L3 Cache or the Ram over those physical interconnects. That requires need the CPU cores to sacrifice memory bandwidth and leads to longer CPU stalls as the cores have to wait idle for memory requests due to the reduction in available bandwidth for the CPU

The tests shown above show real world throughput that includes the Latency overhead cause by the Rams need to operate with appropriate timings.

Conversely, Intel Ringbus ties L3 cache speed to the Ring topology interconnect and also transfers data at 32 bytes/cycle yet, with a Cache multiplier of x42, it gives the transport, that also has to share the bandwidth between CPU and GPU memory needs, a total theoretical bandwidth of 144GB/s providing a surplus of bandwidth that is shared between CPU and GPU to access memory.
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post #46 of 279 (permalink) Old 07-10-2019, 02:36 AM - Thread Starter
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Ryzen 9 3900X results



With 2xCCD read bandwidth is no longer penalized in asynchronous mode but keeps scaling with both fabric and memory clock.





As expected with 2xCCD write bandwidth is approximately doubled. Similarly to the read bandwidth scenario, asynchronous mode does not longer seem to reduce the write bandwidth.





Copy bandwidth gets a nice boost from the increased write bandwidth with 2xCCD.





Memory latency is the same in both cases.
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Last edited by elmor; 07-10-2019 at 02:49 AM.
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post #47 of 279 (permalink) Old 07-10-2019, 03:09 AM
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@elmor

+rep for above share .

From my R5 3600 it seems that 3600MHz 1:1 is very easy to have on Matisse. I'd setup 3533MHz using The Stilt's 3466MHz timings last night, I only had to bump VDIMM from 1.35V to 1.355V. I manually set SOC same as what I saw at default, set CLDO_VDDG ~40mV below SOC.

AIDA64 Bench (Latency is higher than PR though at same clocks/timings, etc)

Spoiler!


RAM Test 1200% last night

Spoiler!


RAM Test 2400% on full POST after shutdown overnight.

Spoiler!


Same POST rerun RAM Test 1200%

Spoiler!


2406_R5_Base_3600S_setting.txt
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post #48 of 279 (permalink) Old 07-10-2019, 03:28 AM
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Quote: Originally Posted by elmor View Post
Plug and Play Gen4 on X470 apparently. Futuremark System Info doesn't seem to detect PCI-E Gen properly.

Max theoretical bandwidth

PCI-E Gen3 x16 = 0.985*16 = 15.8 GB/s
PCI-E Gen4 x16 = 1.969*16 = 31.5 GB/s
Should we be concerned about this being removed in the next BIOS update on the Crosshair VII? I love the board but it would be pretty frustrating if I had to choose between AGESA >1.0.0.2 and PCI-E Gen4 on the first x16 and M.2 slot.
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post #49 of 279 (permalink) Old 07-10-2019, 03:49 AM - Thread Starter
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Quote: Originally Posted by mito1172 View Post
@elmor

Hello. is the article here real?

No Asus Motherboards Officially Support the R9 3900x

https://old.reddit.com/r/Amd/comment...upport_the_r9/

Seems baseless to me, I think they're just behind on qualification. Technically the CPUs are already working on most boards, past and present.

Quote: Originally Posted by Haelous View Post
Should we be concerned about this being removed in the next BIOS update on the Crosshair VII? I love the board but it would be pretty frustrating if I had to choose between AGESA >1.0.0.2 and PCI-E Gen4 on the first x16 and M.2 slot.

It's a possibility, we'll just have to wait and see. Enabling it by default is puzzling, would be better if it's an opt-in setting as it can't be guaranteed to work.
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post #50 of 279 (permalink) Old 07-10-2019, 04:10 AM
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Are we going to see those Aida latency numbers come down? My best/stable 3600MHz setup is high 57ns low 58ns with the 2700X.

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