Over 40 hours of messing with the DRAM Calculator & watching "Buildzoid" videos, buying new stuff he recommended and I have had NO PROGRESS -- PLZHELP!! Ryzen 3950x RAM - Page 11 - Overclock.net - An Overclocking Community
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Over 40 hours of messing with the DRAM Calculator & watching "Buildzoid" videos, buying new stuff he recommended and I have had NO PROGRESS -- PLZHELP!! Ryzen 3950x RAM

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post #101 of 107 (permalink) Old 05-22-2020, 06:14 AM - Thread Starter
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Quote: Originally Posted by Veii View Post
Long thread, much time has passed since then @negativefusion
Sadly i didn't see any explanation to why to do things how they are done
Rares picture was solid and cLDO_VDDP of 700mV is a good entry point, it's not needed to be pushed higher
No one here goes for 1920FLCK or higher to even consider having a bump on these

Tho Nighthog's suggestions all are solid
I missed only the mention of
"Higher ProcODT will decrease maximum FLCK your cpu can run, increase memory controller stress and it does scale up with used VSOC
Less vSOC, less maximum procODT before too early cutoff happens"

I see no where mentioned higher AddCmdDrvStrengh - the first CAD_BUS value,
~ does help allowing lower procODT to run, at the exchange of required higher VDIMM

The 3rd value to be 24 should only be used if you face cold boot issues
20 is great and it helps signal integrity
All of these resistance and impedance values should remain low, same for voltage issues
Start low - i'm sorry back then it was not understandable what i mean
Low VDDP , low procODT, low CAD_BUS, low RTT values
Low everything is needed to preseve signal integrity and so increase the chance of higher MT/s to work

MT/s = mega transfers per sec - memory isn't in Mhz it's in MT/s , because DDR = double data rate
Only mhz is MemoryClock, MCLK - or FLCK , fabric Clock

One rule you have to keep in mind is:
Higher VDIMM requires higher cut-off resistance
This means, higher procODT and this also means higher CAD_BUS and potencialy RTT values ~ which are memory drive impedance ones

If TM5 passes, be it anta or 1usmus - the issue belongs likely to the CPU
This means,
it can be the voltage range just being predicted dumb, it can be PBO doing nonsense with the boosting voltage curve
It can be bad vSOC, and it can be just higher stress to the sillicon - requiring , well you guess it vSOC bump
Tho vSOC bump harms signal integrity soo lower is always better = remain voltages need to be lower else nothing will work

If you relate back to the first pages, rares should've linked the page which i gave a big set of voltage patterns to use
Voltages can be used many, but the pattern between them is important
Messing up this pattern can and potencialy will choke the provided current, making memory controller and cpu freq stability issues
"You shouldn't use PBO while overclocking memory - no wonder, as you shouldn't modify CPU behavior when working with memory, because they are linked"

CAD_BUS 40-20-24-24 does work borderline with low procODT
CAD_BUS 48-20-24-24 works rarely, because procODT most of the times is too low, or VDIMM is too low and it will refuse to post
In order for 60-20-24-24 or higher to work, you will need to fix other values
Dual rank should use between 60-120ohm for the first value, 4x dual rank will need to help the board with VDDG IOD and procODT to tame the higher stress
X570 should be fine with a tiny bit of VDDG IOD bump - up to brand and memory stress, but when you increase procODT you kill any chance to even near 1900FLCK, as you worsen signal integrity

Likely DRAM Calculator had many fixes, as it suplied a very experimental but needed option, which is PCB Layer calculation added into tRFC and some timings
Micron Rev E have couple of node sizes between them, there is no one timing fits all - but they mostly behave identical
About the voltage for them, it depends on the PCB these kits are on, and the nm size this rev. E are on
Sometimes 1.42v is the upper limit, sometimes 1.46v before you see negative results
Current micron mystery kit i work with which is on A2 PCB but from 2017 - loves 1.48v , it hates 1.5 and has negative scaling on 1.52
While A2 PCB loves voltages ~ a bothersome kit, tho CL14-18-22 works well with it

Micron kits love tRCD RD , and it does scale a bit with voltage
But what really scales with voltage is tCL and tRP
Where when tRP scales, tRAS and tRC will scale - soo tRFC will scale logically too down with it

This post is gotta get long i feel,
Micron Kits some like tRC*10 the worst ones, others love *8 , it depends on many factors PCB revision included
tRFC on the dram calculator is accurate, this tRC multiplied by something over tCL/2 exists to hit a stable sync, but it remains an Estimation of voltage drop what the correct value is
1usmus's presets on the DRAM calculator, the R-XMP tested presets, have different low tRFC values
They are pretested with pretested math, the rulesets are factored in - but it's been finetuned, soo the values look off

You do calculate tRFC by tRC in nanosec
Calculating tRC * something, is a good ETA, but because timings are virtual values and placeholders of big 8digit decimal nanosecounds values
Math will be wrong, if you do it that way
Use this for future reference
https://docs.google.com/spreadsheets...cx9WdReTsnIWw/
The Copy sheet has a manual mode for experienced users who know what to look for
It's not the ultimate resolve like 1usmus does it, but it's helpful

tRAS remains tCL+tRCD something
this something depends on how you scale timings up
tRDWR & tWRRD guide was written here
https://www.overclock.net/forum/10-a...l#post28385690
The logic remains, but Dual Rank kits need higher tWRRD & tRDWR
You can't use the -1 tRDWR tweak to bump of efficiency, like you can do on single ranked kits
Math's else the same , just give it +2 on tRDWR to cover dual rank
Never touch tCWL if you use this method of calculation
it will make issues if tCWL is not = tCL

GDM is not hard
Enabling it, will turn virtual timings into even
It is helpful on many parts, but if you want to run exotic timings - and odd ones like tCL15 , you have to fix your kit to work with GDM off
But GDM off will have a far higher stress to the memory, soo when you know how to calculate your timings - i suggest 2T over GDM enabled
Else to make things easy, enable GDM and stay with even values
example 16-18-22-18-38-56-560tRFC

tWR and tRTP work together, but tWR has more calculation methods
tRTP should be optimally half of tWR , but it also should be optimally a clean divider (non decimal or .5) of tRFC
tWR optimally has to be a clean divider of tRFC too, but you can use these formulas:
~ tRAS-tRCD (smallest) = maximum range
~ tCL+tRTP = should not be used but can for high capacity where tRTP is high ~ used only for exceptions
~ tRRDS+tWTRS = used as minimum value, never drop under this one - but for it to work, you should have no where wasted latency between timings

tRC optimally should be tRAS+tRP
it can be down to -2 to lower tRFC, but this exception will fail if you have wasted latency anywhere else

tRAS has no wiggle room unless small exception
it always has to be at least tCL+tRCD
Examples:
If you use a set of 14-12-22-18-36
You can either use tCL+22 making it maximum tRAS of 36
or you can use smaller tRAS of the middle between these two 12 & 22 the middle value is 17
What will still work is tCL+17= 31, optimally 32

you have to keep in mind, here you waste latency - but memory remains in an waiting-for-action loop if you have wasted latency somewhere
Soo people often push tRC as +2 or +4 values for high speeds and worse kits, to givethem enough latency soo cells can recharge in time (tRP value)
Or sometimes just to have a clean working tRFC

tRFC can be high, but if you want snappiness you keep up a clean sync
As it will desync after time - and the board + the ryzen 3rd gen do autocorrect timings
(they are a mess to begin with soo they need some auto correction of some sort)
Suggestion is, go back to the post at the start and find my voltage patterns to fix the cpu , before you go further tightening timings
Hi, I also took a break from this for the last week, as it was becoming too much with absolutely no progress being made.

Thanks for all that... it's a huge dump of information overload, and 95% of it sadly went over my head.

Considering the late reply, I am not exactly sure what settings you are commenting/replying for when you tell me to not tighten and instead "fix the cpu with voltage patterns"?

I went over the first few pages, I have no idea what "voltage patterns" you are talking about... is this it? This is what @rares495 linked - https://www.overclock.net/showthread...4#post28424814 If so, I again, have no idea what you expect me to do with this information. This link + your response was completely information overload.

The problem right now is not "tightening timings", I have a few different problems with a few different "settings".

For example, throughout the thread, and with @Nighthog 's help - I was able to get 1, ONE, set of CL15 timing stable with GDM off - but as you saw from that picture, that setting only booted about 15% of time (useless, as I am not going to sit and mash the power button a dozen times, and then clear CMOS, only to restore a profile every day just to get back into windows, that isn't an option, that's just dumb). So from that "stable" (if you call it that), I tried a bunch of different settings as proposed by @Nighthog - none of them worked to help fix the boot problem while being allowed to pass stability tests.

He also said (like you) GDM Off is hard and to go to GDM ON, so I did (above), tried CL16 at 3733, at CL 16... loose... (see picture) - these settings are with PBO OFF and loose, but trying to tighten them at all (for example the RED #s) == instability, but the RED #s worked before with the CL15 with GDMOFF ...

Tried the junk output from Ryzen Dram calculator 1.7.0, 1.7.1 1.7.2 and even 1.7.3 -- i even made a post in the DRAM calc saying the calc still seems very buggy, and based on "imported XMP" (not generic), i get junk settings like this second picture (CL 14 @ 3733 @ 1.4volts) << is this possible? Everything I have read tells me "NO 3733c14 is impossible @ 1.42v".

So there is a bunch of different builds I have attempted, and I dont even know at this stage where to even begin trying to process your information... what build... what setting, from what stage? For example, do I go back to the CL15 build that passed SEVENTEEN HOURS of Kahru, AND Tm5, but fails PBO and fails to boot 85% of the time?? and try to fix THAT? If so, how?

Do I go to the CL16 build I linked above?

I was also told that apparently my motherboard could be the problem as its a "workstation board" even though its rated at 4400+ Memory OC!

I definitly do not want to start at step 1 again, I have already wasted over 80 hours on this with absolutely no progress, none.

My current options are:
3733c16 Loose timings that I cant seem to tighten
3733c15 tight fixed timings that don't boot 85% of the time, and fails PBO practically instantly even when it does boot.
3733c14 junk output for REV-E from the calculator that doesn't even post at the settings

So as you can see, I have actually gotten nowhere, literally not a single variation of a build "better than XMP" has been stable, there has always been something wrong with any setting...

Thanks again for your reply ... let me know if you have any specifc tips/tricks to focus on to help me with......anything here.
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post #102 of 107 (permalink) Old 05-23-2020, 10:27 PM
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Timing are below. They are calculated as 2400MT/s, 2666MT/s and 2800MT/s which should be tight enough if you run your RAM at 3600MT/s to begin with. You must find a set of settings that your RAM and IMC are working well together, then you can try higher frequencies if you like, you will always have a working set to return to.

I don't know how good is your CPU's IMC, so I have marked IMC timings as *IMC, you can try the timings I'm suggesting and see if they work for you.

2400MT/s:
Spoiler!



2600MT/s:
Spoiler!


2800MT/s
Spoiler!


I have only tuned the primaries according to what I have seen working for your RAM. G.skill, Crucial...etc. always tune the primaries and program the rest according to RAM manufacturers' datasheet when storing the timings in an XMP profile.

Everybody can calculate RAM timings if they wish to, it's not a secret, I have provided the method long ago which you can read here: LINK
All you need is RAM datasheet and an excel-ark. Members make a big deal of it because they don't know where those numbers come from.

Just a side note: tRC has nothing to do with tRFC, the first is a raw cycle for memory access (access column, access row, operation (read/write) and close) which has to complete before the RAM is again ready for access, whereas tRFC is a refresh of stored data while any operation is stopped and cells holding charges (represent 1, opposite to 0 for cells with no charge) are recharged, this is done to maintain data integrity because cells lose electricity overtime.

I hope that you can make use of the posted timings or calculate them in the future.

Give a man RAM timings and he will use them once, teach a man how to calculate them and he will calculate them every time.
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post #103 of 107 (permalink) Old 05-24-2020, 12:48 PM - Thread Starter
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Quote: Originally Posted by Ramad View Post
Timing are below. They are calculated as 2400MT/s, 2666MT/s and 2800MT/s which should be tight enough if you run your RAM at 3600MT/s to begin with. You must find a set of settings that your RAM and IMC are working well together, then you can try higher frequencies if you like, you will always have a working set to return to.

I don't know how good is your CPU's IMC, so I have marked IMC timings as *IMC, you can try the timings I'm suggesting and see if they work for you.

2400MT/s:
Spoiler!



2600MT/s:
Spoiler!


2800MT/s
Spoiler!


I have only tuned the primaries according to what I have seen working for your RAM. G.skill, Crucial...etc. always tune the primaries and program the rest according to RAM manufacturers' datasheet when storing the timings in an XMP profile.

Everybody can calculate RAM timings if they wish to, it's not a secret, I have provided the method long ago which you can read here: LINK
All you need is RAM datasheet and an excel-ark. Members make a big deal of it because they don't know where those numbers come from.

Just a side note: tRC has nothing to do with tRFC, the first is a raw cycle for memory access (access column, access row, operation (read/write) and close) which has to complete before the RAM is again ready for access, whereas tRFC is a refresh of stored data while any operation is stopped and cells holding charges (represent 1, opposite to 0 for cells with no charge) are recharged, this is done to maintain data integrity because cells lose electricity overtime.

I hope that you can make use of the posted timings or calculate them in the future.

Give a man RAM timings and he will use them once, teach a man how to calculate them and he will calculate them every time.
I don't really understand what any of this means, my XMP profile out of the box is already 3600MHZ 16-18-18-18 - but you are giving me timings that run at 2400, 2600 , and 2800? I thought the goal was trying to get to 3733 that @Nighthog and @rares495 were trying to help with?

I am really not sure what to do with any of this information, why would I downclock my ram from 3600 stable at CL16 to ... 2400CL16 or 2600CL16 or 2800CL16 ? I already had a 3000 MHZ Kit that was fine at XMP 3000, I got rid of it to buy this 3600 KIT...

Not to mention the FCLK hit, my old 3000MHZ XMP ram meant my FCLK was at 1500, that's why I got the new kit, so FCLK is at 1800 out of the box. This 2400CL16, 2600CL16, and 2800CL16 would mean my FCLK would be lower than my old kit. Why would I do that?

Thanks
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post #104 of 107 (permalink) Old 05-24-2020, 08:57 PM
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Quote: Originally Posted by negativefusion View Post
I don't really understand what any of this means, my XMP profile out of the box is already 3600MHZ 16-18-18-18 - but you are giving me timings that run at 2400, 2600 , and 2800? I thought the goal was trying to get to 3733 that @Nighthog and @rares495 were trying to help with?

I am really not sure what to do with any of this information, why would I downclock my ram from 3600 stable at CL16 to ... 2400CL16 or 2600CL16 or 2800CL16 ? I already had a 3000 MHZ Kit that was fine at XMP 3000, I got rid of it to buy this 3600 KIT...

Not to mention the FCLK hit, my old 3000MHZ XMP ram meant my FCLK was at 1500, that's why I got the new kit, so FCLK is at 1800 out of the box. This 2400CL16, 2600CL16, and 2800CL16 would mean my FCLK would be lower than my old kit. Why would I do that?

Thanks

You misunderstood the meaning of my post, I provided the timings of these frequencies so you can use them at higher frequency such as 3600MT/s or 3800MT/s, It's what I wrote in the 2nd sentence of my previous post. These are tighter than your RAM's XMP profile.


More simple said: You take 2400MT/s timings and use them on RAM running at 3800MT/s, this is what tight timings means. It does not mean punching in any lower numbers in the BIOS and hoping for the best. Many of these timings are related so they need to be in sync.



I hope that you now understand the meaning of my previous post.


One last thing, 80% of screenshots (if not more) posted by members at OCN are for show and have never been tested correctly. Trust members that posts screenshots of their stability testings of at least 2 hours of Prime95 or y-cruncher using 80% of available RAM because these programs do stress the CPU, RAM and IMC at the same time.


Best of luck finding the sweet spot for your overclock.
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post #105 of 107 (permalink) Old 05-25-2020, 12:09 AM
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post #106 of 107 (permalink) Old 05-25-2020, 12:37 AM
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@Ramad why would you not tweak tRFC? It has been shown to be one of the most important timings to tighten.
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post #107 of 107 (permalink) Old 05-25-2020, 10:08 AM
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Quote: Originally Posted by Dollar View Post
@Ramad why would you not tweak tRFC? It has been shown to be one of the most important timings to tighten.
It's only worth it on B-die. (from 400 to <260)

Going from 550 to 500 on Rev. E or from 500 to 440 on DJR is not going to bring any noticeable performance increase. The only gain would be better sync. And that does mean better performance but it's rather hard to notice it if there's no immediate gain in the most common tasks. You'd have to rely on benchmarking tools such as SiSoftware Sandra to even see a difference. But such tools are inconsistent and you could say even that tiny increase could be margin of error.

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