There's no reason the same process could not be worked through at 4.7ghz. I'm simply erring on the side of caution with my recommendation since I can't actually have my hands on the problem here from afar. I believe there is a lower risk of running into problems working through the process at a slightly lower clock, as it offers more fudging room for voltage and thermal related stability as the LLC settings are experimented with. It's possible that as this is experimented with, voltage under a load could vary pretty wildly. (+/-0.1V or more may be possible). I also prefer to do this procedure from "round numbers" because it just makes the arithmetic easier come to to layout the road-map. For most other PD chips I would suggest using 4.0ghz to run the same set of tests.