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post #271 of 283 (permalink) Old 05-09-2015, 05:31 PM
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I´ll call Zen as a success if:

- The average IPC increases by 40% or more and IPC in FP workloads increases by 55% or more, over Piledriver
- The base clocks are at least 3.2GHz immediately upon the release on 8 core SKUs
- The desktop platform (socket infrastructure) supports up to 16 cores / 32 threads or alternatively two separate nodes
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post #272 of 283 (permalink) Old 05-09-2015, 06:48 PM
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Zen's real success will be measured by how efficient it is compared to Intel's Skylake. It's intended to be a server part.

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post #273 of 283 (permalink) Old 05-09-2015, 09:17 PM
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Quote:
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Zen's real success will be measured by how efficient it is compared to Intel's Skylake. It's intended to be a server part.
Well acording to Lisa, absolute performance and being competitive with intel matter. So its more than just performance/$ or performance/watt.

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post #274 of 283 (permalink) Old 05-10-2015, 02:58 AM
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Originally Posted by The Stilt View Post

I´ll call Zen as a success if:

- The average IPC increases by 40% or more and IPC in FP workloads increases by 55% or more, over Piledriver
- The base clocks are at least 3.2GHz immediately upon the release on 8 core SKUs
- The desktop platform (socket infrastructure) supports up to 16 cores / 32 threads or alternatively two separate nodes

With 256Bit FPu they should reach 2x FPu performance and thats what they need.
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post #275 of 283 (permalink) Old 05-10-2015, 03:50 AM
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With 256Bit FPu they should reach 2x FPu performance and thats what they need.
x2 if the block diagram is at any way correct. 256 bit floating point is going to be almost 4 times faster, as there are hopefully going to be 2 256-bit float units that each can run one 256-bit float per cycle, vs the construction cores taking two cycles per 256 bit float.

Of course though, i could be completely wrong about it, so take it with a grain of salt.

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post #276 of 283 (permalink) Old 05-10-2015, 03:56 AM
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With 256Bit FPu they should reach 2x FPu performance and thats what they need.

I think it is rather optimistic to expect the FPU performance to double with 256-bit FMAC.

All 15h family cores have two 128-bit FMACs which are automatically either configured to unganged (2 * 128-bit) or ganged (256-bit) mode.
If the "slave core" within a compute unit is shedded the remaining "master core" (BSC) will have both of the FMACs in it´s private disposal.
On Bulldozer this resulted in slight performance boost especially in FP workloads but in later µArch iterations (Piledriver and newer) it makes absolutely no difference.

Why exactly this is, is beyond me.

The 256-bit FMAC is indeed mandatory for Zen as otherwise it will suffer severely when AVX2 will be more common.
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post #277 of 283 (permalink) Old 05-10-2015, 04:09 AM
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Originally Posted by The Stilt View Post

I think it is rather optimistic to expect the FPU performance to double with 256-bit FMAC.

All 15h family cores have two 128-bit FMACs which are automatically either configured to unganged (2 * 128-bit) or ganged (256-bit) mode.
If the "slave core" within a compute unit is shedded the remaining "master core" (BSC) will have both of the FMACs in it´s private disposal.
On Bulldozer this resulted in slight performance boost especially in FP workloads but in later µArch iterations (Piledriver and newer) it makes absolutely no difference.

Why exactly this is, is beyond me.

The 256-bit FMAC is indeed mandatory for Zen as otherwise it will suffer severely when AVX2 will be more common.

Why do you think FPU is mainly for AVX2?
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post #278 of 283 (permalink) Old 05-10-2015, 04:47 AM
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Quote:
Originally Posted by The Stilt View Post

I think it is rather optimistic to expect the FPU performance to double with 256-bit FMAC.

All 15h family cores have two 128-bit FMACs which are automatically either configured to unganged (2 * 128-bit) or ganged (256-bit) mode.
If the "slave core" within a compute unit is shedded the remaining "master core" (BSC) will have both of the FMACs in it´s private disposal.
On Bulldozer this resulted in slight performance boost especially in FP workloads but in later µArch iterations (Piledriver and newer) it makes absolutely no difference.

Why exactly this is, is beyond me.

The 256-bit FMAC is indeed mandatory for Zen as otherwise it will suffer severely when AVX2 will be more common.

AMD Piledriver

Similar microarchitecture to Bulldozer
Supports fused multiply-and-add instructions in both the FMA3 and FMA4 form. FMA3 is compatible with Intel processors. See Wikipedia for a discussion of the incompatibility between these instruction sets.
The throughput of FMA3 instructions is only half as much as the throughput of FMA4 instructions, even though they are doing exactly the same calculations.
Memory writes with the 256-bit AVX registers are exceptionally slow. The measured throughput is 5 - 6 times slower than on the previous model (Bulldozer), and 8 - 9 times slower than two 128-bit writes. No explanation for this has been found. This design flaw is likelty to negate any advantage of using the AVX instruction set.
The problems with cache performance on the Bulldozer seem to have been fixed in the Piledriver


http://www.agner.org/optimize/blog/read.php?i=285

It could be errata. Regardless, I expect a huge boost in FPU performance come Zen.

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post #279 of 283 (permalink) Old 05-10-2015, 04:53 AM
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Why do you think FPU is mainly for AVX2?

I don´t, that was just the simplest example I could think of.
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post #280 of 283 (permalink) Old 05-10-2015, 06:43 AM
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Originally Posted by Nnimrod View Post

Well acording to Lisa, absolute performance and being competitive with intel matter. So its more than just performance/$ or performance/watt.

Realistically performance/watt of a CPU architecture / node combo at desktop/server clocks is basically the same thing as absolute performance.

If you have better perf/watt you can just keep adding cores and clocks until the competing architecture with worse perf/watt can't keep up anymore.

This is especially true for servers where due to the prices big dies aren't as much of an issue.


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