[JEDEC] JEDEC DDR5 & NVDIMM-P Standards Under Development - Overclock.net - An Overclocking Community

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[JEDEC] JEDEC DDR5 & NVDIMM-P Standards Under Development

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post #1 of 32 (permalink) Old 03-31-2017, 07:44 AM - Thread Starter
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ARLINGTON, Va., USA – MARCH 30, 2017 –JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced that development of the widely-anticipated DDR5 (Double Data Rate 5) and NVDIMM-P Design standards is moving forward rapidly.  Publication for both is forecasted for 2018. Industry users will have the opportunity to learn more about each standard at JEDEC’s Server Forum event in Santa Clara, CA on Monday, June 19, 2017.  [...]
 
JEDEC DDR5 memory will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency. These enhancements, combined with a more user-friendly interface for server and client platforms, will enable high performance and improved power management in a wide variety of applications.

 

Some potential features of DDR5

 

 

(Source)


 



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post #2 of 32 (permalink) Old 03-31-2017, 07:53 AM
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Originally Posted by TheBlademaster01 View Post

With DDR5 slated for release in 2020, DDR4 will have a very short span of production it seems...
Six years before the next standard is introduced? That's exacttly as long as DDR3.

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post #3 of 32 (permalink) Old 03-31-2017, 07:55 AM
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Samsung can do 4266mhz at 1.10v ( on ~10nm vs their 20-30nm DDR4 at 1.40v )

Doubling that?

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post #4 of 32 (permalink) Old 03-31-2017, 07:55 AM - Thread Starter
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Six years before the next standard is introduced? That's exacttly as long as DDR3.


​Hmm, could have sworn it was longer, but you're correct. I'll remove that bit.


 



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post #5 of 32 (permalink) Old 03-31-2017, 07:58 AM
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Originally Posted by czin125 View Post

Samsung can do 4266mhz at 1.10v ( on ~10nm vs their 20-30nm DDR4 at 1.40v )

Doubling that?

That's probably not a JEDEC spec which usually stop well before top end speeds.

And "10nm"... rolleyes.gif


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post #6 of 32 (permalink) Old 03-31-2017, 08:02 AM
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Originally Posted by czin125 View Post

Samsung can do 4266mhz at 1.10v ( on ~10nm vs their 20-30nm DDR4 at 1.40v )

Doubling that?

Highly uinlikely. DDR2 JEDEC standard started at 400Mhz,DDR3 JDEC standard started at 800MHz, and DDR4 started at 1600MHz. The quote in the OP says they are looking to double again, so DDR5 would probably start at 3200MHz..

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post #7 of 32 (permalink) Old 03-31-2017, 08:16 AM
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Originally Posted by czin125 View Post

Samsung can do 4266mhz at 1.10v ( on ~10nm vs their 20-30nm DDR4 at 1.40v )

Doubling that?

Remember this is double data rate memory, so 4266MHz as people typically write is is actually 2133MHz in real life. We just do a data transaction on the leading and falling edge of the clock pulse so it has double the data rate of the clock speed. 2133MHz really isnt *that* fast for a raw MHz value. Silicon in many CPUs are topping around 5GHz of real MHz speed (Not just Intel, IBM Power CPUs too and AMD stuff as well). So we could see quite a bit higher raw MHz from DRAM too, though it will most likely come at the cost of additional cycle latency. So in the end real final latency will remain the same as it has since DDR1 (30-50ns depending on model). Though th other possibility is only a very small speed bump, and the rest of the doubling of performance comes from wider transfers or addressing changes due to the stacking nature of the specification. And one last thing to note, though Samsung can do "4266MHz", official JEDEC top speed is still way down at DDR-2667 if I am not mistaken and I believe the launch speed was DDR4-1600 or maybe 1866. So we could see an official launch spec for this new memory of only around DDR-3200 (1600MHz real). That wouldn't stop companies like GSkill and others from launching higher speed memory though, as they always do.



The past I find interesting is that even with the planned stacking of die's JEDEC still only plans double the density of DDR4? This may imply the stacking process requires less dense dies to use, or that the spec may only stack two dies at most.

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post #8 of 32 (permalink) Old 03-31-2017, 08:42 AM
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Why cant we have QDR5?

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post #9 of 32 (permalink) Old 03-31-2017, 09:33 AM
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Why cant we have QDR5?

Thats basically what has been happening since DDR. Double Data Rate. DDR2 is double DDR1 and so on.


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post #10 of 32 (permalink) Old 03-31-2017, 09:40 AM
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