[Guru3d] AMD Working on Vertical (3D) Stacking of DRAM onto processors - Page 2 - Overclock.net - An Overclocking Community

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[Guru3d] AMD Working on Vertical (3D) Stacking of DRAM onto processors

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post #11 of 38 (permalink) Old 03-18-2019, 08:41 AM
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It has been wanted for many many years to have a nice large L4 cache/RAM on CPU. But AMD and Intel barely every make even a CPU with nice L4 cache let alone put RAM on the CPU. Why we still don't have a huge L4 cache on CPUs is beyond me. Putting RAM on CPU... more relevant for mobile use than desktop, server.
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post #12 of 38 (permalink) Old 03-18-2019, 08:50 AM
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Quote: Originally Posted by mmonnin View Post
Yes, it's more expensive. There is an extra logic die and interposer for GPUs with HBM. The image shows at least the interposer + the memory controller being moved off the CPU silicon. TSVs also add extra die space vs conventional RAM. TSVs are more complex with additional processing that can't be tested until the whole stack is complete. 1 chip has a bad TSV? Whole stack of DRAM is tossed.

It does mention 2.5D not 3D so there might not be TSVs between the DRAM/interposer although there are vertical lines straight through the DRAM modules to the interposer.
Quote: Originally Posted by epic1337 View Post
don't forget about HBCC.
theoretically the on-package stacked DRAMs could just be treated as a cache like the eDRAM was, so additional DRAM sticks should be possible.

[IMG]https://images.anandtech.com/doci/11002/Vega%20Final%20Presentation-16_575px.png[IMG]


the main advantage of this is that super-high speed DRAM sticks no longer matter as much, all the latency sensitive high-bandwidth workloads would be done by the on-package DRAM.
they could even go for high-bandwidth configurations like octa-channel instead to allow rapid dump and load between on-package and off-package DRAM, maximizing the on-package DRAM's throughput.
Quote: Originally Posted by Hwgeek View Post
For OEM's and for us as a product it will be much better, less debugging of Ram issues/compatibility with chipset/socket/CPU- just send the CPU for RMA, less power usage/cleaner and simpler MB PCB design.
It's going to be more expensive for us tho- since no more keeping your current memory modules and just upgrading CPU/MB, need to buy all new CPU/MB combo.

Same situation like on GPU's/smartphone's and other devices with memory soldered on board. But for Memory Brands (not the manufacturers) this going to be bad, they will be forced to go for other new products.
Thanks for the info!

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post #13 of 38 (permalink) Old 03-18-2019, 09:12 AM
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How can this be any good for heat transfer? I know of a German guy who actually sanded off his CPU die in order to improve heat transfer. Real story.

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post #14 of 38 (permalink) Old 03-18-2019, 10:00 AM
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intel wasnt planning some 3D Stack RAM on chip??is this similar or is this 2.5D?
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post #15 of 38 (permalink) Old 03-18-2019, 10:06 AM
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If the design was entirely low-TDP (<65W), go for it.

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post #16 of 38 (permalink) Old 03-18-2019, 10:38 AM
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Quote: Originally Posted by mouacyk View Post
If the design was entirely low-TDP (<65W), go for it.
Intel's Lakefield is 7w so I imagine this will compete, the Ryzen 2500u is between 12-25W.

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post #17 of 38 (permalink) Old 03-18-2019, 10:52 AM
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And this is how AMD/Intel (Foveros) differentiate and integrate their IPs vs what Nvidia does as the node continues to shrink.
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post #18 of 38 (permalink) Old 03-18-2019, 01:36 PM
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Quote: Originally Posted by mmonnin View Post
Yes, it's more expensive. There is an extra logic die and interposer for GPUs with HBM. The image shows at least the interposer + the memory controller being moved off the CPU silicon. TSVs also add extra die space vs conventional RAM. TSVs are more complex with additional processing that can't be tested until the whole stack is complete. 1 chip has a bad TSV? Whole stack of DRAM is tossed.

It does mention 2.5D not 3D so there might not be TSVs between the DRAM/interposer although there are vertical lines straight through the DRAM modules to the interposer.
Zen 2 already removed the memory controller from the CPU, so moot point.

That being said, the slide's picture is literally a copy/paste of the Vega HBM2 slide and says GPU on it. The slide also says "On-Die 3D Stacked Memory in Development", so in the future it seems they are hoping to put HBM or DRAM directly onto the Ryzen IO Die.

Also, yes, the HBM stack does need pinouts through the interposer, they need to get power from somewhere and AMD does not use IVRs. However, dies are not attached to the interposer with TSVs, they are micro ball soldered. TSVs are only for the actual RAM to the controller;


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post #19 of 38 (permalink) Old 03-18-2019, 02:06 PM
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Quote: Originally Posted by EastCoast View Post
And this is how AMD/Intel (Foveros) differentiate and integrate their IPs vs what Nvidia does as the node continues to shrink.
You mean like dedicate tensor cores?
Extensive library of features and 3D tech for developers?
G-sync?
3D vision?

Yes, all nvidia are doing is just shrinking.
That is why they are smaller than AM... oh wait.

And considering AMD's rebranding practice, no, they are all doing the same thing.


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post #20 of 38 (permalink) Old 03-18-2019, 02:12 PM
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technically they don't strictly need interposers to do this, Intel's EMIB for example is used to solder AMD's GPU with an HBM chip on-package without a full-die interposer.
the only question is whether Intel has full patent exclusivity over this approach, which i doubt.

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